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EBE25UD6ABFA 参数 Datasheet PDF下载

EBE25UD6ABFA图片预览
型号: EBE25UD6ABFA
PDF下载: 下载PDF文件 查看货源
内容描述: 256MB无缓冲DDR2 SDRAM DIMM [256MB Unbuffered DDR2 SDRAM DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 22 页 / 214 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE25UD6ABFA的Datasheet PDF文件第2页浏览型号EBE25UD6ABFA的Datasheet PDF文件第3页浏览型号EBE25UD6ABFA的Datasheet PDF文件第4页浏览型号EBE25UD6ABFA的Datasheet PDF文件第5页浏览型号EBE25UD6ABFA的Datasheet PDF文件第7页浏览型号EBE25UD6ABFA的Datasheet PDF文件第8页浏览型号EBE25UD6ABFA的Datasheet PDF文件第9页浏览型号EBE25UD6ABFA的Datasheet PDF文件第10页  
EBE25UD6ABFA  
Byte No. Function described  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
15ns  
27  
28  
29  
30  
31  
Minimum row precharge time (tRP)  
Minimum row active to row active  
delay (tRRD)  
Minimum /RAS to /CAS delay (tRCD)  
Minimum active to precharge time  
(tRAS)  
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
3CH  
28H  
3CH  
28H  
40H  
10ns  
15ns  
40ns  
Module rank density  
256M bytes  
Address and command setup time  
32  
before clock (tIS)  
-5C  
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H  
35H  
38H  
48H  
10H  
0.25ns*1  
0.35ns*1  
0.38ns*1  
0.48ns*1  
0.10ns*1  
-4A  
Address and command hold time after  
clock (tIH)  
-5C  
33  
-4A  
Data input setup time before clock  
(tDS)  
-5C  
34  
35  
-4A  
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H  
23H  
0.15ns*1  
0.23ns*1  
Data input hold time after clock (tDH)  
-5C  
-4A  
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H  
3CH  
0.28ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
-5C  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-4A  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
41  
Memory analysis probe characteristics 0  
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
00H  
00H  
37H  
TBD  
Extension of Byte 41 and 42  
0
0
Undefined  
55ns*1  
Active command period (tRC)  
Auto refresh to active/  
42  
43  
44  
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
0
1
0
0
1
0
69H  
80H  
1EH  
23H  
28H  
105ns*1  
8ns*1  
Auto refresh command cycle (tRFC)  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-5C  
0.30ns*1  
0.35ns*1  
0.40ns*1  
-4A  
Data hold skew (tQHS)  
-5C  
-4A  
45  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
2DH  
00H  
00H  
10H  
0.45ns*1  
46  
PLL relock time  
Undefined  
47 to 61  
62  
SPD Revision  
Rev. 1.0  
Checksum for bytes 0 to 62  
-5C  
-4A  
63  
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
1
79H  
FDH  
7FH  
Continuation  
code  
64 to 65  
Manufacturer’s JEDEC ID code  
66  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FEH  
00H  
Elpida Memory  
67 to 71  
Preliminary Data Sheet E0534E11 (Ver. 1.1)  
6