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EBE21UE8AADA 参数 Datasheet PDF下载

EBE21UE8AADA图片预览
型号: EBE21UE8AADA
PDF下载: 下载PDF文件 查看货源
内容描述: 2GB DDR2 SDRAM SO- DIMM [2GB DDR2 SDRAM SO-DIMM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 21 页 / 205 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBE21UE8AADA的Datasheet PDF文件第2页浏览型号EBE21UE8AADA的Datasheet PDF文件第3页浏览型号EBE21UE8AADA的Datasheet PDF文件第4页浏览型号EBE21UE8AADA的Datasheet PDF文件第5页浏览型号EBE21UE8AADA的Datasheet PDF文件第7页浏览型号EBE21UE8AADA的Datasheet PDF文件第8页浏览型号EBE21UE8AADA的Datasheet PDF文件第9页浏览型号EBE21UE8AADA的Datasheet PDF文件第10页  
EBE21UE8AADA  
Byte No. Function described  
Minimum active to precharge time  
(tRAS)  
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value  
Comments  
45ns  
30  
0
0
1
0
1
1
0
1
2DH  
-5C  
-4A  
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
28H  
01H  
40ns  
31  
32  
Module rank density  
1G bytes  
Address and command setup time  
before clock (tIS)  
-5C  
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
25H  
35H  
38H  
48H  
10H  
0.25ns*1  
0.35ns*1  
0.38ns*1  
0.48ns*1  
0.10ns*1  
-4A  
Address and command hold time after  
clock (tIH)  
33  
-5C  
-4A  
Data input setup time before clock  
(tDS)  
-5C  
34  
35  
-4A  
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
15H  
23H  
0.15ns*1  
0.23ns*1  
Data input hold time after clock (tDH)  
-5C  
-4A  
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
28H  
3CH  
0.28ns*1  
15ns*1  
36  
37  
Write recovery time (tWR)  
Internal write to read command delay  
(tWTR)  
-5C  
0
0
0
1
1
1
1
0
1EH  
7.5ns*1  
-4A  
0
0
0
0
1
0
0
1
1
1
0
1
0
1
0
0
28H  
1EH  
10ns*1  
7.5ns*1  
Internal read to precharge command  
delay (tRTP)  
38  
39  
40  
Memory analysis probe characteristics 0  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00H  
00H  
TBD  
Extension of Byte 41 and 42  
0
0
0
0
1
0
0
0
Undefined  
Active command period (tRC)  
-5C  
41  
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
3CH  
37H  
7FH  
80H  
1EH  
23H  
28H  
60ns*1  
-4A  
55ns*1  
Auto refresh to active/  
42  
43  
44  
127.5ns*1  
8ns*1  
Auto refresh command cycle (tRFC)  
SDRAM tCK cycle max. (tCK max.)  
Dout to DQS skew  
-5C  
0.30ns*1  
0.35ns*1  
0.40ns*1  
-4A  
Data hold skew (tQHS)  
-5C  
45  
-4A  
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
2DH  
00H  
00H  
12H  
0.45ns*1  
46  
PLL relock time  
Undefined  
47 to 61  
62  
SPD Revision  
Rev. 1.2  
Checksum for bytes 0 to 62  
-5C  
63  
0
1
0
1
1
1
1
1
1
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
65H  
DFH  
7FH  
FEH  
-4A  
Continuation  
code  
64 to 65  
66  
Manufacturer’s JEDEC ID code  
Manufacturer’s JEDEC ID code  
Elpida Memory  
Preliminary Data Sheet E0767E10 (Ver. 1.0)  
6