EBE21UE8AADA
Serial PD Matrix
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Comments
128 bytes
Number of bytes utilized by module
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
80H
08H
manufacturer
Total number of bytes in serial PD
device
256 bytes
2
3
4
5
6
7
8
Memory type
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
08H
0EH
0AH
71H
40H
00H
05H
DDR2 SDRAM
Number of row address
Number of column address
Number of DIMM ranks
Module data width
14
10
Stack / 2ranks
64
Module data width continuation
0
Voltage interface level of this assembly 0
SSTL 1.8V
DDR SDRAM cycle time, CL = 5
9
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
3DH
50H
50H
3.75ns*1
5.0ns*1
0.5ns*1
-5C
-4A
0
0
SDRAM access from clock (tAC)
-5C
10
-4A
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
60H
00H
82H
08H
00H
00H
0.6ns*1
None.
7.8µs
× 8
11
12
13
14
15
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
Reserved
None.
0
SDRAM device attributes:
Burst length supported
16
17
18
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0CH
08H
38H
4,8
SDRAM device attributes: Number of
banks on SDRAM device
8
SDRAM device attributes:
/CAS latency
3, 4, 5
19
20
21
DIMM Mechanical Characteristics
DIMM type information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
01H
04H
00H
3.80mm max.
SO-DIMM
Normal
SDRAM module attributes
Weak Driver
50Ω ODT
Support
22
23
SDRAM device attributes: General
0
0
0
0
0
0
1
1
03H
Minimum clock cycle time at CL = 4
-5C
0
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
3DH
50H
3.75ns*1
5.0ns*1
-4A
Maximum data access time (tAC) from
clock at CL = 4
-5C
24
0
1
0
1
0
0
0
0
50H
0.5ns*1
-4A
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
60H
50H
0.6ns*1
5.0ns*1
25
26
27
28
29
Minimum clock cycle time at CL = 3
Maximum data access time (tAC) from
clock at CL = 3
0
0
0
0
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
60H
3CH
1EH
3CH
0.6ns*1
15ns
Minimum row precharge time (tRP)
Minimum row active to row active
delay (tRRD)
7.5ns
15ns
Minimum /RAS to /CAS delay (tRCD)
Preliminary Data Sheet E0767E10 (Ver. 1.0)
5
ELPIDA [ ELPIDA MEMORY ]
