EBE11UE6ACSA
Block Diagram
R
S2
S2
ODT1
ODT0
CKE1
R
R
S2
R
S2
R
S2
CKE0
/CS1
R
S2
/CS0
/CS CKE ODT
/LDQS
/CS CKE ODT
/LDQS
/CS CKE ODT
/CS CKE ODT
/LDQS
R
S1
R
S1
R
S1
R
S1
R
S1
R
S1
/DQS0
DQS0
DM0
/DQS4
DQS4
DM4
/LDQS
LDQS
LDM
LDQS
LDM
LDQS
LDM
LDQS
LDM
8
8
8
R
R
R
R
R
R
S1
S1
S1
S1
S1
I/O0 to I/O7
I/O0 to I/O7
/UDQS
DQ0 to DQ7
/DQS1
DQ32 to DQ39
/DQS5
I/O0 to I/O7 D2
D6
I/O0 to I/O7
S1
/UDQS
D0
D4
/UDQS
/UDQS
R
S1
R
S1
R
S1
UDQS
UDM
UDQS
UDM
DQS1
DQS5
UDQS
UDM
UDQS
UDM
DM1
DM5
8
R
S1
DQ8 to DQ15
I/O8 to I/O15
I/O8 to I/O15
DQ40 to DQ47
I/O8 to I/O15
I/O8 to I/O15
/CS CKE ODT
/LDQS
/CS CKE ODT
/LDQS
/CS CKE ODT
/LDQS
/CS CKE ODT
/LDQS
R
S1
R
S1
R
S1
R
S1
R
S1
R
S1
/DQS2
/DQS6
DQS2
DM2
DQS6
DM6
LDQS
LDM
LDQS
LDM
LDQS
LDM
LDQS
LDM
8
8
8
8
R
R
R
R
R
S1
S1
S1
S1
S1
I/O0 to I/O7
I/O0 to I/O7
DQ16 to DQ23
DQ48 to DQ55
I/O0 to I/O7 D3
D7
I/O0 to I/O7
R
S1
R
S1
R
S1
/UDQS
UDQS
D1
/UDQS
UDQS
D5
/DQS3
DQS3
DM3
/DQS7
DQS7
DM7
/UDQS
/UDQS
UDQS
UDM
UDQS
UDM
UDM
UDM
R
S1
R
S1
DQ24 to DQ31
I/O8 to I/O15
I/O8 to I/O15
DQ56 to DQ63
I/O8 to I/O15
I/O8 to I/O15
R
R
S2
BA0 to BA2
A0 to A12
BA0 to BA2: SDRAMs (D0 to D7)
A0 to A12: SDRAMs (D0 to D7)
Serial PD
SDA
S2
R
S2
R
S2
R
S2
SCL
SCL
A0
SDA
/RAS
/CAS
/WE
/RAS: SDRAMs (D0 to D7)
/CAS: SDRAMs (D0 to D7)
/WE: SDRAMs (D0 to D7)
SA0
SA1
U0
A1
A2
WP
CK0
4 loads
4 loads
/CK0
CK1
/CK1
Notes :
1. DQ wiring may be changed within a byte.
VDDSPD
VREF
SPD
SDRAMs (D0 to D7)
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
must be meintained as shown.
VDD
SDRAMs (D0 to D7) VDD and VDDQ
SDRAMs (D0 to D7) SPD
VSS
* D0 to D7 : 1G bits DDR2 SDRAM
U0 : 2k bits EEPROM
Rs1 : 22
Ω
Rs2 : 3.0
Ω
Data Sheet E1045E20 (Ver. 2.0)
8
ELPIDA [ ELPIDA MEMORY ]
