C9950
Maximum Ratings[5]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any volt-
age higher than the maximum rated voltages to this circuit. For
proper operation, Vin and Vout should be constrained to the
range:
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection .............................................. 2 KV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic volt-
age level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V ±5%, TA = –40°C to +85°C
Parameter
VIL
Description
Input Low Voltage
Conditions
Min.
Typ.
Max.
Unit
V
0.8
VIH
Input High Voltage
2.0
V
IIL
Input Low Current (@VIL = VSS
)
Note 6
Note 6
–120
120
0.5
µA
µA
V
IIH
Input High Current (@VIL =VDD
Output Low Voltage
)
VOL
VOH
IDDC
IDD
IOL = 40 mA, Note 7
IOH = –40 mA, Note 7
All VDDC and VDD
VDD only
Output High Voltage
2.4
V
Quiescent Supply Current
PLL Supply Current
15
15
20
20
4
mA
mA
pF
Cin
Input Capacitance
AC Parameters[8]: VDD = VDDC = 3.3V ±5%, TA = –40°C to +85°C
Parameter
Tr/Tf
Description
TCLK Input Rise/Fall
Conditions
Min.
Typ.
Max.
Unit
ns
3.0
Fref
Reference Input Frequency
Crystal Oscillator Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Note 9
10
Note 2
MHz
MHz
%
Fxtal
See Table 3 for details
25
FrefDC
Fvco
25
75
200
480
MHz
ms
Tlock
Tr/Tf
Maximum PLL lock Time
Output Clocks Rise/Fall Time[10]
10
0.8V to 2.0V
QA = (÷2)
0.10
1.0
ns
Fout
Maximum Output Frequency
180
MHz
QA/QB = (÷4)
QB = (÷8)
120
60
FoutDC
Output Duty Cycle
TCYCLE/2 – 1
TCYCLE/2 + 1
ns
ns
ns
ps
ps
tpZL, tpZH Output enable time (all outputs)
tpLZ, tpHZ Output disable time (all outputs)
6
7
TCCJ
Cycle to Cycle Jitter (peak to peak)[10]
Any Output to Any Output Skew[10]
±100
200
TSKEW0
350
Notes:
5. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. Inputs have internal pull-up/pull-down resistors that affect input current.
7. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / under
shoot.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. Maximum and minimum input reference is limited by the VCO lock range.
10. Outputs loaded with 30 pF each.
Document #: 38-07072 Rev. *C
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