C9950
the outputs Q(B:D) depending on the configuration (see Table
2). The use of even dividers ensures that the output duty cycle
remains at 50%.
Description
The C9950 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
The PLL is ensured stable operation given that the VCO is
configured to run between 200 MHz and 480 MHz. This allows
a wide range of output frequencies from 25 MHz to 180 MHz.
The internal VCO frequency is divided by 8 or 16 and com-
pared to the input reference clock. These selectable dividers
allow for input reference clock flexibility. The internal VCO is
running at 2x or 4x the high speed output (QA), and 4x or 8x
Output Frequency
The C9950 generates outputs with programmable frequency
relationships. As a result, the input reference frequency is a
function of the desired output frequency (Table 1). The follow-
ing block diagram illustrates the corresponding parameters
that are needed to calculate the output frequency.
VCO
/N
Fref
Qn
Phase
Detector
LPF
/m
Figure 1.
Fref = FVCO/m, FVCO = FQn x N
Fref = (FQn x N) / m
Where m = 8 (FB_SEL = 1) or m = 16 (FB_SEL = 0), and N = 2, 4, or 8 depending on SEL_ as shown in Table 1.
Table 2.
INPUTS
OUTPUTS
SELA
SELB
SELC
SELD
QA
QB
QC
QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/2
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/4
VCO/4
VCO/8
VCO/8
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/4
VCO/8
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
VCO/4
VCO/8
Document #: 38-07072 Rev. *C
Page 3 of 7
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