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C9819ATB 参数 Datasheet PDF下载

C9819ATB图片预览
型号: C9819ATB
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 17 页 / 198 K
品牌: CYPRESS [ CYPRESS ]
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+/+when timing is critical  
C9819  
133 MHz I2C Clock Generator for Mobile Pentium®III / Rambus Systems  
Preliminary  
Power Management Timing  
Tss  
Tss  
PCI_F  
PCI_STP  
PCI(0:6)  
CPU_STP  
CPU  
Fig. 4  
Tss is the stop clock setup time. All functionality is referenced to the rising edge of PCI_F. If the tss timing is met, with  
respect to the next occurring PCI_F low to high transition, then the CPU or PCI clocks that are controlled are guaranteed  
to stay low (stopped) or to rise (run) at the next rising edge of PCI_F. See the AC parameters for tss time.  
Power Management Function Table  
CPU_stp#  
PWRDN#  
PCI_stp  
#
CPU  
CPU/2  
3V66(0:2)  
PCI(0:6)  
PCI_F  
48M /  
REF(0:2)  
IOAPIC(0:1)  
PLL1  
PLL2  
x
0
0
1
1
0
1
1
1
1
x
0
1
0
1
0
0
0
run  
run  
0
0
0
0
run  
0
0
0
0
off  
off  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
run  
Table 2  
2-Wire I2C Control Interface  
The 2-wire control interface implements a write slave only interface according to Philips I2C specification. (see fig5). The  
device cannot be read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to change  
one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100  
Kbits/second (standard mode) data transfer is supported.  
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is  
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the  
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer  
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer  
cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode .  
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on  
the SDATA wire following reception of each byte.  
INTERNATIONAL MICROCIRCUITS, INC 525 LOS COCHES ST.  
MILPITAS, CA 95035, USA TEL: 408-263-6300 FAX 408-263-6571  
Rev 1.0  
11/1/1999  
Page 5 of 17  
http://www.imicorp.com