+/+…when timing is critical
C9819
133 MHz I2C Clock Generator for Mobile Pentium®III / Rambus Systems
Preliminary
Vdd
Strapping Resistor Options:
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high
Rup
50K
IMI C9819
Rd
Load
Bidirectional
selection. In this case, the designer may choose one of
two configurations, see Fig. 3A and Fig. 3B.
JP1
JUMPER
Fig. 3A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows a
faster pull to a high level.
Fig.3A
Rdn
5K
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.4A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
JP2
Vdd
3 Way Jumper
Fig. 3B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Rsel
10K
IMI C9819
Rd
Load
Bidirectional
Fig.3B
Power Management Functions
Power Management on this device is controlled by CPU_STP# (pin28), PCI_STP# (pin29) and PWRDN# (pin23).
When CPU_STP# is forced low, the CPU signal is synchronously (no glitch) disabled in a low state. CPU will complete
the cycle and stop before the next rising edge of the PCI_F clock. This is to ensure synchronous stopping after a full
cycle without any glitches. When CPU_STP# is released to high, CPU is synchronously re-enabled. CPU clock will
start toggling on the rising edge before the rising edge of the PCI_F occurs. This also is to ensure a synchronous start of
a full clock cycle.
When PCI_STP# is forced low, only PCI(0:6) signals are synchronously disabled in a low state. These signals will
complete one full cycle before stopping one the following falling edge. PCI_F is still running. When PCI_STP# is
released to high, PCI(0:6) are synchronously re-enabled after the equivalent of one full PCI cycle latency.
When PWR_DN# is forced low, CPU, PCI(F,0:6), APIC(0:1), 3V66-(0:2), CPU/2, 48MHz, and REF(0:2) signals are
synchronously disabled, all internal circuitry (including the crystal buffer) is shutdown and the device is in Low Power (or
in power down) Mode. After PWRDN# is forced low, all power supplies (3.3V and 2.5V) may be removed. All power
supplies must be re-applied 200mS before releasing PWR_DN# (to high), consequently, the device must be allowed
1mS before the clock outputs settle to their preset frequencies. (see Fig. 4, and table 2 below)
INTERNATIONAL MICROCIRCUITS, INC 525 LOS COCHES ST.
MILPITAS, CA 95035, USA TEL: 408-263-6300 FAX 408-263-6571
Rev 1.0
11/1/1999
Page 4 of 17
http://www.imicorp.com
CYPRESS [ CYPRESS ]
