+/+…when timing is critical
C9815B
Low EMI Clock Generator for Intel 133MHz/2DIMM Chipset Systems
Preliminary
IOAPIC Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Clock Phase Relationships
0nS
10nS
20nS
30nS
40nS
Sync
CPU CLOCK
CPU CLOCK
CPU CLOCK
66MHz
100MHz
133MHz
2.5nS
5nS
0nS
5nS
7.5nS
SDRAM CLOCK
SDRAM CLOCK
100MHz
133MHz
3.75nS
0nS
0nS
3.75nS
3V66 CLOCK
PCI CLOCK
66MHz
33MHz
1.5~3.5nS
IOAPIC CLOCK
33MHz
Fig.3
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.1
3/12/2000
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