+/+
Preliminary
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
…when timing is critical
C9815B
Frequency Table (MHz)
SEL2
X
X
0
0
1
1
SEL1
0
0
1
1
1
1
SEL0
0
1
0
1
0
1
CPU
Tristate
66.6
100
133.3
133.3
Table 1
Low EMI Clock Generator for Intel
®
133MHz/2DIMM Chipset Systems
Meets Intel’s 133MHz/SDRAM chipset specification
3 copies of CPU Clock (CPU[0:1] and CPU2_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
7 copies of PCI Clock
3 copies of 3V66 Clock
2 copies of IOAPIC Clock
1 REF Clock
1 USB Clock (Non SSC)
1 DOT Clock (Non SSC)
IMI Spread Spectrum for best EMI reduction
2
I C Support with read back
56 Pin SSOP package
SDRAM
Tristate
100*
100*
133.3
100*
PCI
Tristate
33.3
33.3
33.3
33.3
Test mode (see table2)
Note: The following clocks remain fixed frequencies
except in Test Mode: 3V66=66.6MHz, USB/DOT=48MHz,
REF=14.318MHz and IOAPIC=33.3MHz.
2
*I C programmable to 133 MHz, Byte 3, Bit 0
Block Diagram
XIN
36pF
300K
36pF
XOUT
1
VDD
REF / SEL2
Pin Configuration
REF/SEL2
VDD
XIN
XOUT
VSS
VSS
3V66_0
3V66_1
3V66_2(AGP)
VDD
VDD
PCI0(ICH)
PCI1
VSS
PCI2
PCI3
VSS
PCI4
PCI5
PCI6
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2(ITP)
VSS
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VSS
DCLK
VDD
PD#
SCLK
SDATA
SEL1
VDDI
s2
apic
2
VDDC
cpu
Rin
SCLK
SDATA
SEL1
SEL0
PD#
i2c-clk
i2c-data
s1
s0
pwr_dwn#
3V66
2
VDD
pci
PLL1
Rin
PD#
1
i2c-clk
i2c-data
PLL2
USB
48
1
VDD
8
VDD
DOT
PCI(0:6)
sdram
9
VDD
3V66(0:2)
VDDS
SDRAM(0:7), DCLK
3
CPU(0:2)
IOAPIC(0:1)
C
9
8
1
5
Fig.1
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.1
3/12/2000
Page 1 of 18
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