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C9809BY 参数 Datasheet PDF下载

C9809BY图片预览
型号: C9809BY
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56]
分类和应用: 光电二极管外围集成电路
文件页数/大小: 20 页 / 349 K
品牌: CYPRESS [ CYPRESS ]
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+/+…when timing is critical  
C9809B  
Low EMI Clock Generator for Intel 133MHz/3DIMM Chipset Systems  
Preliminary  
Power on Bi-Functional Pins (Cont.)  
Pin 30 (TS# / PD#) is a bi-functional pin, See Fig.6. If this pin is externally held low during power up, the device is forced  
into tristate/or test mode depending on the state of Sel0.  
In Tristate mode, all outputs assume the high impedance (Hi-Z) state. In test, all outputs toggle as described in table 2,  
page 3.  
All outputs remain in their Hi-Z state (or test mode) until the external signal applied to pin 30 is released (set high). After  
a minimum of 1.5mS from a stable 3.3V power supply or until TS# is released (whichever is longer), pin 30 changes  
from a tristate controller (TS#) to Power Down controller (PD#) and remains in that function unless otherwise  
programmed through the I2C to return to the TS# function by setting byte3, bit1 to a “0”. Once the TS# signal is released  
(high), pin 30 may be toggled repetitively to force the device in and out of power down mode.  
The device is considered in power down when PD# is asserted low, consequently, all clocks are stopped synchronously  
and after the completion of a full period (glitch-free).  
3.3V  
Power  
Supply  
TS# function  
TS# asserted  
low  
TS# released  
PD# asserted low  
PD# released  
TS#  
ς
TS# function  
Default High  
PD#  
/
ς
I2C,  
Byte3,  
Bit1  
programmed Low  
Toggle  
Hi-Z  
Hi-Z  
Output  
Clock  
Power Down  
ς
ς
Fig.6  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
Rev 1.2  
3/8/2000  
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
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