+/+…when timing is critical
C9809B
Low EMI Clock Generator for Intel 133MHz/3DIMM Chipset Systems
Preliminary
Test Mode Function
Test Mode Functionality
TS#
0
SEL0 CPU (0:1)
SDRAM (0:12)
TCLK/2
3V66 (0:2)
PCI (_F, 1:5)
TCLK/6
DOT/USB
TCLK/2
REF
TCLK
IOAPIC
TCLK/6
Tristate
1
0
TCLK/2
Tristate
TCLK/3
0
Tristate
Tristate
Tristate
Tristate
Tristate
Table 2
Note: TCLK is a test clock over driven on the XIN input during test mode. Test Mode/Tristate mode set during power up
and if TS# is low. Also can be set through I2C when Byte3 bit6 = 1, Byte0 bit0 = 1, and bit4 = 4.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin30). When PD# is high (default) the device is in
normal running mode and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies may be
removed. When in power down, all outputs are synchronously stopped in a low state (see Fig.2 below), all PLL’s are
shut off, and the crystal oscillator is disabled. When the device is shutdown, the I²C function is also disabled.
Power Management Timing
0nS
10nS
20nS
30nS
40nS
50nS
100MHz
CPU
3V66
66MHz
33MHz
33MHz
PCI
IOAPIC
PWRDN#
Undefined
Undefined
Undefined
SDRAM 100MHz
14.3MHz
48MHz
REF
USB
Fig.2
Power Management Current
Maximum 2.5 Volt Current
Consumption (VDDC = VDDI =2.625)
Maximum 3.3 Volt Current Consumption
(VDD = VDDA = VDDS = 3.465 V)
PD#, SEL(3:0)
0XXXX (Power down)
10000 (66MHz)
10mA
70 mA
100 mA
10mA
280 mA
280 mA
365 mA
10001 (100MHz)
1001X (133 MHz)
133 mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before
releasing the PD# pin high.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
3/8/2000
Page 3 of 20
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