C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
Pin Description
PIN No.
Pin Name
TYPE
I/O
Description
2
This is a bi-directional pin with an internal pull-up. The direction of this pin is determined by
the state of signal MODE (pin 7).
REF0 /
CPU_STP#
If Mode = 0, this pin is a CPU_STP# input pin. When CPU_STP# is asserted low, CPU and
CPU-OD are forced LOW and CPU# is in Tristate.
If Mode = 1, this pin is REF0, a buffer output of the signal applied at Xin.
This is the input pin to the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. It may also be driven from an alternative clock
source.
This is the output pin of the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. If Xin is driven from an alternative clock source, then
this pin should be unconnected.
This is a power on bi-directional strapping pin with an internal pull-up(see app note, page 4).
During power up, this pin is an input “Mode” for setting the direction of Pin 2. When the power
reaches the rail, this pin becomes a PCI0 clock output.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S1” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a PCI1 clock output.
4
5
7
8
I
XIN
O
XOUT
I/O
I/O
PCI0 /
MODE
PCI1 /
S1
10,11,12,13
15
40,38,37,35,
34,32,31,29,
28,21,20,18,17
23
OUT
IN
OUT
PCI clock outputs. Synchronous to CPU clocks.
LVTTL Input pin to the SDRAM(0:12) distribution buffers.
SDRAM Buffered Outputs. They are buffered outputs of the signal applied at SDRAMIN.
When PWR_DN# is low. These signals are forced low regardless of the signal at SDRAMIN.
PCI(2:5)
SDRAMIN
SDRAM (0:12)
I/O
Serial data input pin.
Conforms to the Philips I2C specification of
a
Slave
SDATA
Receiver/Transmitter device. This pin is an input when receiving data. It is an open drain
output when acknowledging or transmitting. See I2C function description, p.8.
Serial clock input pin. Conforms to the Philips I2C 100KHz Specification
This is a power on bi-directional strapping pin with an internal pull-down (see app note, page
4). During power up, this pin is an input “S3” for frequency selection, see table 1, p.1. When
the power reaches the rail, this pin becomes a SIO clock output programmed to 24MHz or
48MHz via byte3, bit6 in the I2C table. It defaults to 24MHz.
24
25
I
SCLK
24_48MHz / S3
I/O
26
I/O
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S2” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a 48MHz, USB clock output.
This is an open drain output, for system reset. See detailed description , p.___
Open Drain Differential CPU outputs. They require external pull-up to 1.5V. See table 1 page
1 for frequency selection.
48MHz /
S2
41
43, 44
SReset
CPU, CPU#
O
46
48
O
Open Drain single ended CPU clock. It requires an external pull-up to 3.3V. It is in phase with
CPU clock (pin 43).
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S0” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a REF1, a buffered clock output of the signal applied
at Xin.
CPU-OD
IN/OUT
REF1 / S0
1,6,14,27, 42
19, 36, 30
3, 9, 16, 22, 33, 39,
45, 47
PWR
PWR
GND
Common 3.3V Power Supply.
Power supply for SDRAM. Nominally 3.3V
Ground
VDD
VDDS
VSS
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 2 of 17
CYPRESS [ CYPRESS ]
