C9707
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Preliminary
Serial Control Registers
NOTE: The Pin # column lists the affected pin number where applicable. The @Pup column gives the state of the
control register at power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte. Must be programmed to FF for correct operation.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
Byte2,…) will be valid and acknowledged.
Byte 0: Frequency Control Register (1 = Enable, 0 = Low)
Bit @Pup Pin# Pin Description
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
See Table 3 below
S2
S1
S0
1 = enable byte 0, bits 6, 5, 4, 2, 1 for frequency selection table 4
S4
S3
See Table 3 below
Byte 1: CPU / SDRAM Clock Register (1=Enable, 0=Low)
Bit @Pup Pin# Pin Description
7
6
5
4
3
2
1
0
0
0
0
0
1
0
1
1
-
-
-
-
40
-
SBW2 (See SST Page 5, Table 3)
SBW1 (See SST Page 5, Table 3)
SBW0 (See SST Page 5, Table 3)
Reserved
SDRAM12
Reserved
43,44
46
CPU,CPU# (0 = disabled, CPU in low and CPU# in Hi-Z mode)
CPU-OD
Byte0, Bit 7 Byte0, Bit0
Modes
0
0
1
1
0
1
0
1
Normal operation
Tri-state
Spread Spectrum On
Test mode (Spread Spectrum On)
Table 3
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571
http://www.imicorp.com
Rev 1.2
4/25/2000
Page 8 of 17
CYPRESS [ CYPRESS ]
