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C9641AT 参数 Datasheet PDF下载

C9641AT图片预览
型号: C9641AT
PDF下载: 下载PDF文件 查看货源
内容描述: [Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 18 页 / 244 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
C9641  
133 MHz Clock Generator for ALI 1641 Chipset Systems  
Pin Description (Cont.)  
PIN No.  
Pin Name  
IOAPIC  
TYPE  
OUT  
Description  
46  
14.31818 MHz, 2.5V clock output. This output is used to clock the CPU communication bus  
in multi processor systems.  
48  
IN /  
OUT  
This is a power on bi-directional pin with an internal pull-up. During power up, this pin is an  
input “FS1” for setting the CPU frequency (see table1, page 1) (see app not, page 4). When  
the power reaches the rail, this pin becomes a buffered output of the signal applied at Xin  
(typically 14.318 MHz).  
FS2 /  
REF0  
44, 43  
2
9
10  
18, 29, 37  
45  
47  
OUT  
2.5V host bus (CPU) clock outputs. See Table 1 Page 1 for frequency programming.  
3.3V power supply for reference output clocks and crystal circuitry.  
3.3 Volt Power supply for AGP clock.  
3.3V power supply for PCI clocks.  
3.3 Volt Power supply pins for SDRAM's.  
2.5 Volt Power supply pin for CPU (1:0) output buffers.  
2.5 Volt Power supply pin for IOAPIC output.  
Power supply Ground return pins for the device.  
CPU (1:0)  
VDDR  
VDDA  
VDDP  
VDDS  
VDDC  
VDDI  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
PWR  
5, 6, 14, 28,  
33, 41, 42,  
23  
VSS  
26  
PWR  
Power supply pin for the 48 MHz output.  
VDD48  
Internal pull-ups are typically 250K. They may vary between 200Kand 500K.  
Power on Bi-Directional Pins  
Power Up Condition:  
Pins 1, 11, 27, and 48 are Power up bi-directional pins and are used for programming initial power up frequency and  
desktop/mobil mode functions in this device (see Pin description, Page 2). During power-up, these pins are in input mode  
(see Fig 2, below), therefore, they are considered input select pins internal to the IC. After a settling time, the Selection  
data is latched into internal control registers and these pins then become toggling clock outputs.  
VDD Rail  
Power Supply  
Ramp  
FS1/REF1  
FS0/PCI_F  
48_24#MHz/MODE  
FS2/REF0  
-
Hi-Z Inputs  
Toggle Outputs  
Select Data is latched into register then pin becomes clock output signal.  
Fig. 2  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Document#: 38-07037 Rev. **  
5/02/2001  
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