PRELIMINARY
C9641
133 MHz Clock Generator for ALI 1641 Chipset Systems
Pin Description
PIN No.
1
Pin Name
FS1/
TYPE
IN /
OUT
Description
This is a power on bi-directional pin with an internal pull-up. During power up, this pin is an
input “FS1” for setting the CPU frequency (see table1, page 1) (see app note, page 4). When
the power reaches the rail, this pin becomes a buffered output of the signal applied at Xin
(typically 14.318 MHz).
REF1
3
4
IN
Input pin to the crystal oscillator. This pin connects to the crystal lead. It also may serve as
the input to an externally generated clock.
Output pin of the crystal oscillator. This pin connects the crystal lead. When an externally
generated signal is applied to XIN, this pin remains unconnected.
XIN
OUT
XOUT
8, 7
11
OUT
IN /
OUT
AGP clock outputs. They are synchronous to CPU clocks
AGP (1:0)
FS0/
PCI_F
This is a power on bi-directional pin with an internal pull-up. During power up, this pin is an
input “FS0” for setting the CPU frequency (see table1, page 1) (see app note, page 4). When
the power reaches the rail, this pin becomes a PCI clock output. This clock does not stop
when PCI_STP# is asserted low.
17, 16, 15,
13, 12
19
OUT
PCI clock outputs. They are synchronous to CPU clocks.
PCI (1:5)
IN /
OUT
This is a bi-directional pin with an internal pull-up. Its direction is controlled by the state of
“Mode” (pin27).
CPU_STP# /
SDRAM12
If Mode = 1, this pin is an SDRAM12 clock output.
If Mode = 0, this pin is a CPU_STP# input pin. When CPU_STP# is asserted low CPU(0:1)
clocks are synchronously stopped in a low state. (See Power Management Description, page
5.)
20
IN /
OUT
This is a bi-directional pin with an internal pull-up. Its direction is controlled by the state of
“Mode” (pin27).
PCI_STP# /
SDRAM11
If Mode = 1, this pin is an SDRAM11 clock output.
If Mode = 0, this pin is a PCI_STP# input pin. When PCI_STP# is asserted low PCI(1:5)
clocks are synchronously stopped in a low state. (See Power Management Description, page
5.)
21
22
IN /
OUT
This is a bi-directional pin with an internal pull-up. Its direction is controlled by the state of
“Mode” (pin27).
If Mode = 1, this pin is an SDRAM10 clock output.
If Mode = 0, this pin is a PD# input pin. When PD# is asserted low, all clocks are stopped in
a low state. (See Power Management Description, page 5.)
PD# / SDRAM10
IN /
OUT
This is a bi-directional pin with an internal pull-up. Its direction is controlled by the state of
“Mode” (pin27).
AGP_STP# /
SDRAM9
If Mode = 1, this pin is an SDRAM9 clock output.
If Mode = 0, this pin is a AGP_STP# input pin. When AGP_STP# is asserted low, AGP(0:1)
clocks are synchronously stopped in a low state (See Power Management Description, page
5.)
24
25
27
IN
IN
IN /
SCLK
SDATA
MODE / 48_24#
MHz
SMBus compatible SDATA input. Has an internal pull-up (>100KΩ)
SMBus compatible SCLK input. Has an internal pull-up (>100KΩ)
This is a power on bi-directional pin with an internal pull-up. During power up, this pin is an
input “Mode”. (see app not, page 4). If “Mode” is strapped high, then pins 19-22 are SDRAM
(9:12) outputs. If “Mode” is strapped low, the pins 19-22 are inputs and the power
management feature is enabled.
OUT
When the power reaches the rail, this pin becomes a 48_24#Mhz programmable output
clock. The frequency of this output defaults to 48MHz. It may be programmed to 24MHz via
the SMBus bus, Byte 0, Bit0.
30, 31, 32,
34, 35, 36,
38, 39, 40
OUT
SDRAM clock outputs. They are synchronous to CPU clocks.
SDRAM(0:8)
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07037 Rev. **
5/02/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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