C6003B
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, VIN and VOUT should be constrained to the
range: VSS < (VIN or VOUT) < VDD. Unused inputs must always
be tied to an appropriate logic voltage level (either VSS or VDD).
Maximum Ratings
Maximum Input Voltage Relative to VSS .............. VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................... –65° to +150°C
Operating Temperature:...................................... 0° to +70°C
Maximum ESD protection ............................................... 2KV
Maximum Power Supply: ................................................5.5V
Operating Voltage: .................................................2.5 – 3.6V
DC Parameters (VDD = 3.3V ±10%, TA = 0°C to +70°C)
Parameter
VIL
Characteristics
Input Low Voltage
Conditions
SSON, SSSEL
Min.
Typ.
Max.
Units
V
–
2.2
0.3*VDD
–5
–
0.8
VIH
Input High Voltage
–
–
V
VTHXIN
IIL[3]
IIH[3]
IIL[4]
IIH[4]
IDD3.3V
VOL
XIN Threshold Voltage
Input Low Current
0.5*VDD
0.7*VDD
V
SSON# = VSS
SSON# = VDD
SSEL = VSS
0
8
5
20
–7.4
5
µA
µA
µA
µA
mA
V
Input High Current
3
Input Low Current
–36
–5
–16.5
0
Input High Current
SSEL = VDD
No output load
IOL = 4.0 mA
IOH = –4.0 mA
Pins 6 and 8
Pins 4 and 5
SSON, SSSEL
Dynamic Supply Current
Output Low Voltage
Output High Voltage
Input Capacitance
–
12
–
20
0.4
–
–
VOH
2.4
–
–
V
CIN
3
5
pF
pF
kΩ
CX
XIN, XOUT capacitance
Pull-up/Pull-down Resistance
–
3
5
PU/PD
100
200
400
AC Parameters
Parameter
Characteristics
Input Frequency Range
Rise Time[5, 6]
Conditions
Min.
22
–
Typ.
24
1
Max.
Units
IFR
tr
26
2
MHz
ns
ns
%
tf
Fall Time[5, 6]
–
1
2
BW%
BW%
tPU
tDC
tccj
Bandwidth Spread In%
SSON# = 0, SSSEL= 0
SSON# = 0, SSSEL= 1
All output clocks
CL = 15 pF
–
–1
–3
–
–
Bandwidth Spread In%
–
–
%
Power up to Stable Output[7]
Clock Duty Cycle[5, 7]
REFOUT Cycle-to-Cycle Jitter[5, 7]
CLKOUT Cycle-to-Cycle Jitter[5, 7]
–
3
ms
%
45
–
50
-
55
350
250
CL = 15pF
ps
ps
tccj
–
100
Notes:
3. Although internal pull-down and pull-up resisters have a typical value of 200K (range 100K to 400K).
4. In applications, if a crystal is used for the input reference clock, refer to crystal manufacturer’s specifications for the required crystal load capacitor value.
5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. All outputs loaded
with 15 pF.
6. Measured between 0.1*VDD and 0.9*VDD
.
7. Triggering is done at 1.5V.
Ordering Information
Part Number
Package Type
Production Flow
Commercial, 0°C to +70°C
Commercial, 0°C to +70°C
C6003BZ
8-pin SOIC
C6003BZT
8-pin SOIC Tape and Reel
Note:
8. The ordering part number differs from the marking on the actual device.
Document #: 38-07342 Rev. **
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