PRELIMINARY
CYW43340
1. Introduction
1.1 Overview
The Cypress CYW43340 single-chip device provides the highest level of integration for wearables, audio and IoT applications, with
integrated IEEE 802.1 a/b/g/n MAC/baseband/radio, and Bluetooth 4.0. It provides a small form-factor solution with minimal external
components to drive down cost, flexibility in size, form, and function. Comprehensive power management circuitry and software ensure
the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation.
Figure 2 shows the interconnect of all the major physical blocks in the CYW43340 and their associated external interfaces, which are
described in greater detail in the following sections.
Figure 2. Block Diagram
PMU
FLL
Controller
Analog PMU
Clk rst
JTAG
From
WLAN
BT
To
WLAN
BT
BT/FM
WLAN
CLB
PMU
XTAL/Radio/Pads etc
AXI2APB
From
WLAN
To
WLAN
UART
2
BT
BT
I S
SoCSRAM
GCI
RAM
ROM
LTE
LTE
RAM512KB
ROM640KB
PCM
SDIOD
ARMCM3
ARMCM3
ARM CM0
AHB
Bridge
USB20D
HSIC
WLAN
Master
Slave
WLAN
BT Access
AXI2AHB
AHB2AXI
Registers
DMA
RAM
ROM
To
GCI
Chip
RX/TX
BLE
JTAG
Master
To
CLB
Common
CLB
UPI
LCU
GPIO
DOT11MAC (D11)
1x1 11N PHY
Shared LNA
Control
APU
Timers
WD
To
CLB
BlueRF
SWP DIG
Pause
Modem
FM
Receiver
2.4 GHz / 5 GHz Dualband Radio
BT RF
Document Number: 002-14943 Rev. *L
Page 4 of 96
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