CYW20702
1.2 Block Diagram
Figure 2 shows the interconnect of the major CYW20702 physical blocks and associated external interfaces.
Figure 2. Functional Block Diagram
JTAG
ARM7TDMI‐S
DMA
Scan JTAG
Address Decoder
Bus Arb
Trap & Patch
32‐bit AHB
Flash I/F
AHB2EBI
SPI
Master
External
Bus I/F
AHB2MEM
AHB2MEM
RAM
PMU Control
AHB2APB
Remap &
Interrupt
Controller
WD Timer
Pause
ROM
USB
PCM
UART
SW
Timers
GPIO+Aux
JTAG Master
OTP
(128 bytes)
I/O
32‐bit APB
LCU
Port Control
Digital
Modulator
Digital I/O
Buffer
APU
Debug UART
SPI Transport
Calibration &
Control
RF
Bluetooth Radio
Blue RF I/F
Digital Demod
Bit Sync
BT Clk/
Hopper
I2C_Master
FIFO 1
Low Power
Scan
Rx/Tx
Buffer
Blue RF Registers
LPO
COEX
SECI
FIFO 2
PMU
POR
PTU
Document Number: 002-14773 Rev. *L
Page 6 of 55
CYPRESS [ CYPRESS ]
