CYW20737
1.8 Serial Peripheral Interface
The CYW20737 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20737 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,
Table 4, and Table 5. The CYW20737 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20737 can also
act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Table 3. CYW20737 First SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISOa
SPI_CSb
Configured Pin Name
SCL
–
SDA
–
–
–
–
–
–
P33c
–
P32
a. SPIFFY1 MISO should always be P32. Boot ROM does not configure any others.
b. Any GPIO can be used as SPI_CS when SPI 1 is in master mode, and when the SPI slave is not a serial flash.
c. P33 is always SPI_CS when a serial flash is used for non-volatile storage.
Table 4. CYW20737 Second SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CSa
Configured Pin Name
P3
–
P0
P1
P25
–
–
–
–
P4
P24
P27
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 5. CYW20737 Second SPI Set (Slave Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
Configured Pin Name
P3
–
P0
P27
P33
–
P1
–
P2
–
P24
–
P25
–
P26
P32
Document Number: 002-16365 Rev. *C
Page 8 of 36
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