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B9949CA 参数 Datasheet PDF下载

B9949CA图片预览
型号: B9949CA
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 160 - MHz的1:15时钟分配缓冲器 [3.3V 160-MHz 1:15 Clock Distribution Buffer]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 8 页 / 66 K
品牌: CYPRESS [ CYPRESS ]
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B9949  
Maximum Ratings[2]  
This device contains circuitry to protect the inputs against  
damage due to high static voltages or electric field; however,  
precautions should be taken to avoid application of any volt-  
age higher than the maximum rated voltages to this circuit. For  
proper operation, Vin and Vout should be constrained to the  
range:  
Maximum Input Voltage Relative to VSS:............. VSS 0.3V  
Maximum Input Voltage Relative to VDD:............. VDD + 0.3V  
Storage Temperature: ................................65°C to + 150°C  
Operating Temperature:................................40°C to +85°C  
Maximum ESD protection ............................................... 2KV  
Maximum Power Supply: ................................................5.5V  
Maximum Input Current:...................................................±20mA  
VSS < (Vin or Vout) < VDD  
Unused inputs must always be tied to an appropriate logic volt-  
age level (either VSS or VDD).  
DC Parameters: VDDC = 3.3V ±5%, VDD = 3.3V ±5%, TA = 40°C to +85°C  
Parameter  
Description  
Input Low Voltage  
Conditions  
PECL_CLK, Single Ended  
All other inputs  
Min.  
1.49  
VSS  
Typ.  
Max.  
1.825  
0.8  
Unit  
VIL  
V
VIH  
Input High Voltage  
PECL_CLK, Single Ended  
All other inputs  
2.135  
2.0  
2.42  
VDD  
V
IIL  
Input Low Current (@VIL = VSS  
)
Note 3  
100  
100  
µA  
µA  
IIH  
Input High Current (@VIL = VDD)  
VPP  
Peak-to-Peak Input Voltage  
PECL_CLK  
Note 4  
300  
1000  
mV  
VCMR  
Common Mode Range  
PECL_CLK  
VDD 2.0  
VDD 0.6  
V
VOL  
VOH  
IDD  
Output Low Voltage  
Output High Voltage  
Quiescent Supply Current  
Input Capacitance  
IOL = 20 mA, Note 5  
0.4  
V
V
IOH = 20 mA, VDDC = 3.3V, Note 5  
All VDDC and VDD  
2.5  
1
2
4
mA  
pF  
Cin  
Notes:  
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.  
3. Inputs have pull-up/pull-down resistors that effect input current.  
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the Highinput is within the VCMR  
range and the input lies within the VPP specification.  
5. Driving series or parallel terminated 50(or 50to VDD/2) transmission lines.  
Document #: 38-07081 Rev. *C  
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