B9846
AC Parameters VDD2.5V = 2.5V + 5%, TA = 0°C to +70°C [2]
Parameter
fCLK
Description
Operating Clock Frequency
Input Clock Duty Cycle
Test Conditions
Min.
60
Typ.
Max.
Units
MHz
%
170
52
tDC
48
Tr / Tf
tDC
DDR Output Clocks Rise/Fall Edge Rate 20% to 80%
1.0
3.0
V/ns
%
Output Duty Cycle[4]
Single ended output
Measured at 1.4V for 3.3V
outputs. Measured at VDD/2 for
INDC –
2%
–
INDC +
2%
2.5V outputs
tHCS
tPLH
Half-period jitter
Note 9
–100
100
6
ps
ns
Low-to-High Propagation Delay, BUFIN to
Output
1.5
3.5
3.5
tPHL
High-to-Low Propagation Delay, BUFIN to
Output
1.5
6
ns
ps
tSKEW
Any-Output-to-Any-Output Skew
Note 9
150
Notes:
9. Measured at crossing point (VOC). DDRT/C to FBOUT skew is measured at 50% (for FBOUT) and at crossing point (VOC) for DDRT/C.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production. AUTHOR: NO CORRESPONDING FOOTNOTE IN THE TEXT.
Document #: 38-07299 Rev. *A
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