B9846
Pin Description
Pin No.
Pin Name
BUFIN
PWR
I/O
I
Description
10
VDD2.5V
VDD2.5V
Clock Input. 2.5V for DDR-ONLY.
3,7,12,19,23,27
DDR(0:5)T
O
True DDR Clock Outputs. Buffered copy of the signal
applied at BUFIN.
4,8,13,18,22,26
1
DDR(0:5)C
FBOUT
VDD2.5V
VDD2.5V
O
O
Complementary DDR Clock Outputs. Inverted copy of
the signal applied at BUFIN.
Feedback Clock Output. Single ended buffered copy of
the signal applied at BUFIN. This clock is in phase with
the True DDR clock outputs. It is generally used to drive
the DCLKI of chipset memory controller.
16
15
SCLK
I, PU[1] SerialClockInput. ClocksdataatSDATAintotheinternal
register.
SDATA
I/O, PU Serial Data Input. Input data is clocked to the internal
register to enable/disable individual outputs. This
provides flexibility in power management.
5,9,14,17,21,25
2,6,11,20,24,28
VDD2.5
VSS
2.5V power supply
Common ground
VDDD
DDRT (0:5)
DDRC (0:5)
FBOUT
2.5V
4"
60 Ohm
PROBE
16PF
RT = 120 Ohm
4"
60 Ohm
PROBE
PROBE
16PF
10PF
4"
33
60 Ohm
Figure 1. Differential Signal Using Direct Termination Resistor
A bypass capacitor (0.1 µF) should be placed as close as
possible to each positive power pin (< 0.2”). If these bypass
capacitors are not close to the pins their high-frequency
filtering characteristic will be cancelled by the lead inductance
of the traces.
Note:
1. PU = Internal pull-up, typical value of 640KΩ.
Document #: 38-07299 Rev. *A
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