DATA SHEET
Am29F400B
4 Megabit (512 K x 8-Bit/256 K x 16-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— 5.0 volt-only operation for read, erase, and
program operations
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Minimizes system level requirements
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29F400 device
■ Minimum 1,000,000 program/erase cycles per
■ High performance
sector guaranteed
— Access times as fast as 45 ns
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
■ Low power consumption (typical values at
5 MHz)
— 1 µA standby mode current
— 48-pin TSOP
— 20 mA read current (byte mode)
— 28 mA read current (word mode)
— 30 mA program/erase current
— 44-pin SO
— Known Good Die (KGD)
(see publication number 21258)
■ Flexible sector architecture
■ Compatibility with JEDEC standards
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— Pinout and software compatible with single-
power-supply Flash
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Supports full chip erase
— Provides a software method of detecting
program or erase operation completion
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
Sectors can be locked via programming
equipment
■ Erase Suspend/Erase Resume
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Top or bottom boot block configurations available
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
Publication# 21505 Rev: E Amendment: 8
Issue Date: November 11, 2009
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
CYPRESS [ CYPRESS ]
