ACM100
Normal Read Cycle
transaction. The register being read is sampled during the
ACK bit of the DEVICE ADDRESS where the R/W bit is a 1.
This insures that the two halves of the register being read are
consistent as many registers are volatile and can update at
any time - including the time between when the MSBs are
being read out onto the I2C bus and when the LSBs are being
read.
A normal read cycle begins with a write cycle which is
terminated after the REG_ADDR byte. This partial transaction
is required to properly set the REGISTER ADDRESS to the
register being read. Following the new START command and
the DEVICE ADDRESS, the ACM100 will drive the MSBs of
the register onto the SDA line. The I2C bus master must then
provide an ACK bit for that byte. If the I2C master does not
provide ACK the readback data, then the ACM100 I2C
interface will return to the IDLE state and wait for a new
START. The ACM100 will then drive the LSBs onto the SDA
line and then the I2C bus master can either issue a STOP
command or just not ACK the byte to end the transaction. The
REGISTER ADDRESS is not automatically incremented after
each byte so only one register can be read during each
The REGISTER ADDRESS remains loaded with whatever the
last value was sent. Thus, a write followed by a read of the
same register does not require reloading the REGISTER
ADDRESS. Instead, a START and the DEVICE ADDRESS
with R/W set 1 can immediately follow the DATA LSB of the
write transaction. Note that there is no noise immunity
protection on setting the REGISTER ADDRESS.
Figure 9. Normal Read Cycle
S
DEVICE ADDR
0
A
REG ADDR A S DEVICE ADDR
1
A
DATA MSB
A
DATA LSB
P
Normal Read
A
S
P
A
START
STOP
ACKnowledge from SLAVE
ACKnowledge from MASTER
Noise Immune Reads
corrupted the I2C transaction. Note that the register data is
always consistent as long as the bytes are read out without
initiating a new I2C transaction (IE: a new START/STOP). If
the bytes have been corrupted, the DATA MSB and DATA LSB
fields can simply be read again as the register is not re-read
unless a new DEVICE ADDRESS is issued. Note that this
mode is backwards compatible with older versions of the
ACM100 as reading the ones-complement of the register data
is optional.
Noise immune reads are supported by reading the data bytes
multiple times within the same I2C transaction. Figure 10
shows that the data in the register is sampled during the ACK
bit of the DEVICE ADDRESS. The data is then read out during
the DATA MSB and DATA LSB cycles. If additional bytes are
read out, the ones-complement of the data can be read in
sequence. The data can be compared by the I2C bus master
to insure that the data is correct and that noise has not
Figure 10. Noise Immune Reads
SAMPLE
S
DEVICE ADDR
0
A
REG ADDR A S DEVICE ADDR
1
A
DATA MSB
A
DATA LSB
A
DATA MSB
A
DATA LSB
P
Noise Immune Read
A
S
P
A
START
STOP
ACKnowledge from SLAVE
ACKnowledge from MASTER
Connector Definition
as to the availability of other connectors should your
application require a different connector. The following table
defines the connector pins for the Hirose connector.
The standard camera comes with a pigtail connector
terminated with a Hirose GT17VSN-6DP-HU. Please inquire
Number
Signal
I2C_SDAT
PWR_IN_A
GND
Pins Required
Wire Color
Green
Red
1
2
3
4
5
6
1
1
1
1
1
1
Blue
I2C_SCLK
GND
Gray
Yellow
White
NTSC_OUT
Document Number: 001-05325 Rev. **
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