ACM100
Normal Write Cycle
that is being written to. The ACM100 will assert ACK indicating
rd
that the address has been accepted. The 3 byte of the
A normal write cycle is shown in Figure 7 below. The
transaction begins with a START condition and then the
DEVICE ADDRESS and then the READ/WRITE bit which
must be 0. The ACM100 will acknowledge that it is ready for
the transaction by asserting ACK low shortly after the falling
edge of SCLK during the READ/WRITE bit. The ACM100 will
tristate SDAT so the pullup can bring SDAT high shortly after
the next falling edge of SCLK.
transaction are the most significant bits (MSB) of the register
being written to (bits 15:8). The 4th byte is the least significant
bits (LSBs) of the register being written to (bits 7:0).
The command is terminated with a STOP condition.
Alternatively, another START command can be initiated at this
point. Note that the register is updated when the STOP (or
another START) condition is recognized. All 16 bits of the
register are updated at the same time
nd
The 2 byte of a transaction is the REGISTER ADDRESS
byte which is the address of the register within the ACM100
Figure 7. Normal Write Cycle
S DEVICE ADDR 0 A REG ADDR DATA MSB
A
A
DATA LSB
A P
Normal Write
S
P
A
START
STOP
ACKnowledge from SLAVE
Noise Immune Write
checksum byte be included for all write transactions. This
mode is off by default which makes I2C writes compatible with
previous versions of the ACM100. The register is updated
during the ACK bit of the CHECKSUM byte if the checksum is
correct. The ACM100 will not acknowledge the CHECKSUM
byte if the transaction has been corrupted and the checksum
does not match the computed checksum. The lack of the ACK
in this case can be used as an indicator by the I2C bus master
that the transaction has been corrupted and should be retried.
The I2C bus is susceptible to noise when run on a cable or
even across a long distance on a PCB. To protect the camera
operation in potentially noisy environments, the ACM100 has
a feature that insures that I2C writes are only performed if the
data is correct. A normal write cycle is performed as in the
previous section but an additional byte of data is transferred
which is a checksum of the REGISTER ADDRESS and the two
data bytes. The checksum is easily computed on a
microcontroller using the following formula:
When the checksum mode is enabled (REG9[0]=1) then the
checksum is required and writes will no longer be compatible
with previous versions of the ACM100. This mode insures that
all writes have a good checksum. When the backwards
compatible mode is disabled, the checksum byte is optional.
CHECKSUM = 0xFF + REGISTER_ADDRESS + DATA_MSB
+ DATA_LSB
TFigure 8 below shows the sequence of bytes to insure a valid
register write in the presence of noise on the I2C bus. Note
that register REG9 bit 0 will enable the mode that requires the
Figure 8. Noise Immune Write
S DEVICE ADDR 0 A REG ADDR A DATA MSB A DATA LSB
A
CHECKSUM A P
Noise Immune Write
S
P
A
START
STOP
ACKnowledge from SLAVE
Document Number: 001-05325 Rev. **
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