CY7C185
Switching Characteristics Over the Operating Range[6]
7C185-15
Min. Max.
7C185-20
Min. Max.
7C185-25
Min. Max.
7C185-35
Min. Max.
Parameter
Read Cycle
tRC
Description
Unit
Read Cycle Time
15
3
20
5
25
5
35
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE1 LOW to Data Valid
CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[7]
CE1 LOW to Low Z[8]
CE2 HIGH to Low Z
15
20
25
35
tOHA
tACE1
15
15
8
20
20
9
25
25
12
35
35
15
tACE2
tDOE
tLZOE
3
3
3
3
tHZOE
tLZCE1
tLZCE2
tHZCE
7
7
8
8
10
10
10
10
3
3
5
3
5
3
5
3
CE1 HIGH to High Z[7, 8]
CE2 LOW to High Z
tPU
tPD
CE1 LOW to Power-Up
CE2 to HIGH to Power-Up
0
0
0
0
ns
ns
CE1 HIGH to Power-Down
CE2 LOW to Power-Down
15
20
20
20
Write Cycle[9]
tWC
Write Cycle Time
15
12
12
12
0
20
15
15
15
0
25
20
20
20
0
35
20
20
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE1
tSCE2
tAW
CE1 LOW to Write End
CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tHA
tSA
0
0
0
0
tPWE
tSD
12
8
15
10
0
15
10
0
20
12
0
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[7]
tHD
0
tHZWE
7
7
7
8
tLZWE
WE HIGH to Low Z
3
5
5
5
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE1 and tLZCE2 for any given device.
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05043 Rev. *A
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