CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
[15, 23]
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA
IN
DATA VALID
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
C132-10
[15, 24]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)
t
WC
ADDRESS
CE
t
t
HA
SCE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA
IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
D
OUT
C132-11
Notes:
23. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD
.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
8
CYPRESS [ CYPRESS ]
