CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms
[20, 21]
Read Cycle No. 1 (Either Port-Address Access)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C132-7
[20, 22]
Read Cycle No. 2 (Either Port-CE/OE)
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
C132-8
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
n
t
RC
ADDRESS
ADDRESS MATCH
R
t
PWE
R/W
R
D
INR
VALID
t
PS
ADDRESS MATCH
ADDRESS
L
t
BHA
BUSY
L
t
t
BDD
BLA
DOUT
VALID
L
t
DDD
t
WDD
C132-9
Notes:
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = VIL and OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
7
CYPRESS [ CYPRESS ]
