CY7C1019BV33
AC Test Loads and Waveforms
R1 480
ALL INPUT PULSES
90%
10%
Ω
R1 480
Ω
3.3V
3.3V
3.0V
GND
90%
10%
OUTPUT
OUTPUT
R2
255
R2
255
30 pF
5 pF
Ω
Ω
3 ns
3 ns
≤
≤
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(b)
1019BV33–3
(a)
1019BV33–4
THÉ
VENIN EQUIVALENT
Equivalent to:
167
Ω
1.73V
OUTPUT
Switching Characteristics[4] Over the Operating Range
7C1019BV33-10
7C1019BV33-12
7C1019BV33-15
Parameter
Description
Min.
10
3
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
10
12
15
AA
3
3
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
10
5
12
6
15
7
0
3
0
0
3
0
0
3
0
[5, 6]
OE HIGH to High Z
5
5
6
6
7
7
[6]
CE LOW to Low Z
[5, 6]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
10
12
15
PD
[7, 8]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
10
8
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
7
8
0
0
HA
0
0
0
SA
7
8
10
8
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
5
6
0
0
0
HD
[6]
WE HIGH to Low Z
3
3
3
LZWE
HZWE
[5, 6]
WE LOW to High Z
5
6
7
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CELOW and WE LOW. CE and WEmust be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
3
CYPRESS [ CYPRESS ]
