CY7C4261
CY7C4271
Switching Waveforms (continued)
Reset Timing[16]
t
RS
RS
t
t
t
t
RSR
RSS
REN1,
REN2
RSR
RSS
WEN1
t
t
RSR
RSS
WEN2/LD [18]
t
RSF
RSF
RSF
EF,PAE
FF,PAF
t
t
[17]
OE = 1
Q
Q
8
0 -
OE = 0
First Data Word Latency after Reset with Read and Write
WCLK
t
DS
D –D
D (FIRST VALID WRITE)
D
1
D
2
D
3
D
4
0
8
0
t
ENS
[19]
t
WEN1
FRL
WEN2
(if applicable)
t
SKEW1
RCLK
t
REF
[20]
EF
t
A
t
A
REN1,
REN2
Q –Q
D
0
D
1
0
8
t
OLZ
t
OE
OE
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
for the programmable flag offset registers.
19. When t
> minimum specification, t
(maximum) = t
+ t
. When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
SKEW1 CLK
SKEW1
FRL
CLK
SKEW2
SKEW2
FRL
CLK
+ t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06015 Rev. *C
Page 9 of 18
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