CY7C4261
CY7C4271
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
t
t
WFF
WFF
FF
[14]
t
SKEW1
RCLK
REN1, REN2
Read Cycle Timing
t
CKL
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN1, REN2
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[15]
SKEW1
t
WCLK
WEN1
WEN2
Notes:
14. t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time
SKEW1
between the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
15. t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time
SKEW1
between the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW2
Document #: 38-06015 Rev. *C
Page 8 of 18
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