STK12C68-5 (SMD5962-94599)
Pinouts
Figure 1. Pin Diagram - 28-Pin CDIP
Figure 2. Pin Diagram - 28-Pin LCC
VCAP
A12
1
2
3
28
VCC
27
26
25
WE
HSB
A7
A6
A5
A4
4
5
6
A8
A9
24
23
22
A11
7
A3
A2
OE
A10
(TOP)
8
21
20
9
A1
A0
CE
DQ7
10
19
18
11
12
13
DQ6
DQ5
DQ4
DQ0
DQ1
17
16
15
DQ2
VSS
14
DQ3
Pin Definitions
Pin Name Alt
IO Type
Description
Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
A0–A12
Input
DQ0-DQ7
WE
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
W
E
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
CE
OE
Input
Output Enable, Active LOW. The active LOW OEinput enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tristate.
G
VSS
VCC
Ground
Ground for the Device. The device is connected to ground of the system.
Power Supply Power Supply Inputs to the Device.
Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in
progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A
weak internal pull up resistor keeps this pin high if not connected (connection optional).
HSB
VCAP
Power Supply AutoStoreCapacitor. Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-51026 Rev. *C
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