Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
C
GATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
LOWER THRESHOLD
TYP
UPPER THRESHOLD
THRESHOLD ACCURACY
MIN
MAX
MIN
TYP
MAX
UNITS
% of Nominal DAC Output
-12
-8.5
-5
5
8.5
12
%
ꢀ DAC CODE
VID4 VID3 VID2 VID1 VID0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
1.487
1.443
1.399
1.355
1.311
1.267
1.223
1.179
1.097
1.546
1.501
1.455
1.409
1.363
1.318
1.272
1.226
1.141
1.606
1.558
1.511
1.463
1.416
1.368
1.321
1.273
1.185
1.775
1.722
1.670
1.617
1.565
1.512
1.460
1.407
1.309
1.834
1.779
1.725
1.671
1.617
1.562
1.508
1.454
1.353
1.893
1.837
1.781
1.724
1.669
1.613
1.557
1.501
1.397
V
V
V
V
V
V
V
V
V
Note 1: Guaranteed by design, not 100% tested in production.
Block Diagram
V
CC
-
V
CC
7µA
V
Monitor
CC
+
20k
3.95V
3.87V
ENABLE
-
Circuit Bias
+
V
GATE(H)
Enable
Comparator
SS Low
Comparator
1.25V
5V
-
FAULT
R
Q
Q
PGnd
+
FAULT
S
60µA
0.7V
FAULT
Latch
V
CC
SS High
Comparator
SS
+
-
2µA
V
GATE(L)
2.5V
COMP
V
V
ID0
Error Amplifier
PGnd
+
ID1
5 BIT
DAC
V
-
ID2
ID3
ID4
-
PWM Comp
Blanking
GATE(H) = ON
GATE(H) = OFF
V
V
Maximum
Q
Q
R
S
+
On-Time
Timeout
PWM
Comparator
-8.5% +8.5%
C
OFF
Normal
PWM
Latch
One Shot
+
+
Off-Time
-
-
R
Extended
Off-Time
Timeout
C
OFF
Off-Time
Timeout
S
Q
PWRGD
65µs
Delay
Time Out
Timer
(30µs)
Edge Triggered
V
-
FB
+
V
Low
FB
Comparator
1V
LGnd
6
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
