Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 20V; 2.8V DAC Code (VID4=VID2=VID1=VID0=1, VID3= 0),
GATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ꢀ VCC Supply Current
Operating
1V < VFB < VDAC (max on-time)
No Loads on Gate(H) and Gate(L)
12
20
mA
µA
Sleep Mode
ENABLE = 0V, 8V< VCC <14V
300
600
ꢀ VCC Monitor
Start Threshold
GATE(H) Switching
3.75
3.65
3.95
4.15
4.05
V
Stop Threshold
Hysteresis
GATE(H) not switching
Start - Stop
3.87
80
V
mV
ꢀ Error Amplifier
VFB Bias Current
VFB = 0V
0.1
30
1.0
60
µA
µA
V
COMP Source Current
COMP CLAMP Voltage
COMP = 1.2V to 3.6V; VFB = 2.7V
VFB = 2.7V, Adjust COMP voltage for
Comp current = 50µA
COMP = 0V
15
0.85
1.0
1.15
COMP Clamp Current
COMP Sink Current
Open Loop Gain
0.4
180
50
1.0
400
60
1.6
mA
µA
V
COMP =1.2V; VFB = 3V; VSS > 2.5V
800
Note 1
Note 1
Note 1
dB
Unity Gain Bandwidth
PSRR @ 1kHZ
0.5
60
2
MHz
dB
85
ꢀ GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Measure VCC-GATE
Measure GATE
1.2
1.0
2.0
1.5
V
V
1.6V < GATE < (VCC- 2.5V),
8V < VCC < 14V
40
40
65
80
ns
ns
ns
Fall Time
(VCC - 2.5V) > GATE > 1.6V,
8V < VCC < 14V
80
GATE(H) to GATE(L) Delay GATE(H) < 2V, GATE(L) > 2V,
8V < VCC < 14V
30
100
GATE(L) to GATE(H) Delay GATE(L) < 2V, GATE(H) > 2V,
8V < VCC < 14V
30
20
65
50
100
115
ns
GATE pull-down
Resistance to PGnd (note 1)
kΩ
ꢀ Fault Protection
SS Charge Time
VFB = 0V
1.6
25
3.3
100
3.3
5.0
200
6.0
ms
ms
%
SS Pulse Period
VFB = 0V
SS Duty Cycle
(Charge Time/Period) × 100
VFB = 2.7V, VSS = 0V
Increase VFB till no SS
pulsing and normal Off-time.
1.0
0.50
0.9
SS Comp Clamp Voltage
VFB Low Comparator
0.95
1.0
1.10
1.1
V
V
ꢀ PWM Comparator
Transient Response
VFB = 1.2 to 5V 500ns after
GATE(H) (after Blanking time) to
GATE(H) = (VCC - 1V) to 1V,
8V < VCC < 14V
100
150
ns
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
