Absolute Maximum Ratings
Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° to 150°C
Lead Temperature Soldering:
Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec max. above 183°C, 230°C Peak
Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
VMAX
VMIN
ISOURCE
ISINK
Pin Symbol
Pin Name
VCC
IC Power Input
16V
-0.3V
N/A
1.5A Peak
200mA DC
SS
Soft Start Capacitor
6V
6V
6V
6V
-0.3V
-0.3V
-0.3V
-0.3V
200µA
10mA
10µA
1mA
10µA
1mA
COMP
VFB
Compensation Capacitor
Voltage Feedback Input
Off-Time Capacitor
10µA
50mA
COFF
VID0-4
Voltage ID DAC Inputs
High-Side FET Driver
6V
-0.3V
-0.3V
1mA
10µA
GATE(H)
16V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
GATE(L)
Low-Side FET Driver
16V
-0.3V
1.5A Peak;
200mA DC
1.5A Peak;
200mA DC
ENABLE
PWRGD
PGnd
Enable Input
6V
6V
0V
-0.3V
-0.3V
0V
100µA
10µA
1mA
30mA
N/A
Power-Good Output
Power Ground
1.5A Peak
200mA DC
LGnd
Logic Ground
0V
0V
100mA
N/A
Package Pin Description
FUNCTION
PACKAGE PIN #
PIN SYMBOL
1,2,3,4,6
VID0 -VID4
Voltage ID DAC inputs. These pins are internally pulled up to 5V if left open.
VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp ref-
erence range is 2.14V to 3.54V with 100mV increments. When VID4 is low (logic
zero), the Error amp reference voltage is 1.34V to 2.09V with 50mV increments.
5
7
8
SS
Soft Start Pin. A capacitor from this pin to LGnd sets the Soft Start and fault
timing.
COFF
Off-Time Capacitor Pin. A capacitor from this pin to LGnd sets both the nor-
mal and extended off time.
Output Enable Input. This pin is internally pulled up to 1.8V. A logic Low
( < 0.8V) on this pin disables operation and places the CS5165 into a low cur-
rent sleep mode.
ENABLE
9
VCC
Input Power Supply Pin.
10
11
12
13
GATE(H)
PGnd
GATE(L)
PWRGD
High Side Switch FET driver pin.
High Current ground for the GATE(H) and GATE(L) pins.
Low Side Synchronous FET driver pin.
Power Good Output. Open collector output drives low when VFB is out of
regulation. Active when ENABLE input is low
14
15
LGnd
COMP
Reference ground. All control circuits are referenced to this pin.
Error Amp output. PWM Comparator reference input. A capacitor to LGnd
provides Error Amp compensation.
16
VFB
Error Amp, PWM Comparator, and Low VFB Comparator feedback input.
2
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
