Block Diagram
V
CC2
VCC1 Monitor
Comparator
V
-
CC1
V
GATE
5V
SS Low
+
Comparator
-
FAULT
FAULT
3.90V
3.85V
R
S
Q
Q
+
PGnd
60µA
2µA
0.7V
FAULT
SS
Latch
SS High
Comparator
+
-
V
V
ID0
ID1
2.5V
Error
4 BIT
DAC
Amplifier
+
-
V
V
ID2
ID3
PWM
Comparator
-
GATE = ON
GATE = OFF
R
S
Q
Q
Maximum
On-Time
Timeout
+
Slow Feedback
Fast Feedback
V
FB
PWM
Latch
C
Normal
Off-Time
Timeout
COMP
OFF
One Shot
R
C
OFF
Extended
Off-Time
Timeout
V
FFB
Off-Time
Timeout
-
S
Q
+
V
Low
FFB
LGnd
Comparator
1V
PWM
Time Out
Timer
COMP
Edge Triggered
(30µs)
Applications Information
2
™
The V
control method is illustrated in Figure 1. The out-
Theory of Operation
Control Method
put voltage is used to generate both the error signal and the
ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regard-
less of the origin of that change. The ramp signal also con-
tains the DC portion of the output voltage, which allows
the control circuit to drive the main switch to 0% or 100%
duty cycle as required.
2
™
V
2
™
The V
method of control uses a ramp signal that is gen-
erated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is gen-
erated from the output voltage itself. This control scheme
differs from traditional techniques such as voltage mode,
which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
A change in line voltage changes the current ramp in the
2
™
inductor, affecting the ramp signal, which causes the V
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
2
™
current mode control, the V
control scheme has the
PWM
same advantages in line transient response.
Comparator
+
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined
only by the comparator response time and the transition
speed of the main switch. The reaction time to an output
load step has no relation to the crossover frequency of the
error signal loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this ‘slow’ feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote sens-
V
GATE
C
–
Ramp
Signal
V
FFB
Output
Voltage
Feedback
V
Error
Amplifier
FB
–
+
COMP
E
Reference
Voltage
Error
Signal
2
™
Figure 1: V
Control Diagram
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
