Application Information
cycle greater than 50%. The artificial ramp also ensures the
Theory Of Operation
proper PWM function when the output ripple voltage is
inadequate. The slope compensation signal is properly
sized to serve it purposes without sacrificing the transient
response speed.
V2TM Control
The CS5141X family of buck regulators provides leading
edge technology, a high level of integration and high oper-
ating frequencies allowing the layout of a switch-mode
power supply in a very small board area. These devices are
Under load and line transient, not only the ramp signal
changes, but more significantly the DC component of the
feedback voltage varies proportionally to the output volt-
age. FFB path connects both signals directly to the PWM
comparator. This allows instant modulation of the duty
cycle to counteract any output voltage deviations. The
transient response time is independent of the error amplifi-
er bandwidth. This eliminates the delay associated with
error amplifier and greatly improves the transient
response time. The error amplifier is used here to ensure
excellent DC accuracy.
TM
TM
based on the proprietary V2 control architecture. V2
control uses the output voltage and its ripple as the ramp
signal, providing an ease of use not generally associated
with voltage or current mode control. Improved line regu-
lation, load regulation and very fast transient response are
also major advantages.
Error Amplifier
L1
S1
V
IN
V
O
The CS5141X has a tranconductance error amplifier, whose
non-inverting input is connected to an INTERNAL REFER-
ENCE VOLTAGE generated from the on-chip regulator.
The inverting input connects to the VFB pin. The output of
the error amplifier is made available at the VC pin. A typi-
cal frequency compensation requires only a 0.1µF capacitor
connected between the VC pin and ground, as shown in the
Application Circuit. This capacitor and error amplifier’s
output resistance (approximately 8MΩ) create a low fre-
quency pole to limit the bandwidth. Since V2TM control does
not require a high bandwidth error amplifier, the frequen-
cy compensation is greatly simplified.
R1
C1
Duty
Cycle
D1
Buck
Controller
Slope
Comp
Oscillator
+
FFB
Latch
R
S
R2
The VC pin is clamped below OUTPUT HIGH VOLTAGE.
This allows the regulator to recover quickly from over cur-
rent or short circuit conditions.
+
−
SFB
−
+
V
C
V
REF
+
−
PWM
Comparator
Oscillator and Sync Feature (CS51411 and CS51413 only)
Error Amplifier
2
The on-chip oscillator is trimmed at the factory and
requires no external components for frequency control.
The high switching frequency allows smaller external com-
ponents to be used, resulting in a board area and cost sav-
ings. The tight frequency tolerance simplifies magnetic
components selection. The switching frequency is reduced
to 25% of the nominal value when the VFB pin voltage is
below FREQUENCY FOLDBACK THRESHOLD. In short
circuit or over-load conditions, this reduces the power dis-
sipation of the IC and external components.
V
Control
Figure 1: Buck converter with V2TM control.
As shown in Figure 1, there are two voltage feedback paths
in V2TM control, namely FFB(Fast Feedback) and SFB(Slow
Feedback). In FFB path, the feedback voltage connects
directly to the PWM comparator. This feedback path car-
ries the ramp signal as well as the output DC voltage.
Artificial ramp derived from oscillator is added to the
feedback signal to improve stability. The other feedback
path SFB connects the feedback voltage to the error ampli-
fier whose output VC feeds to the other input of the PWM
comparator. In a constant frequency mode, the oscillator
signal sets the output latch and turns on the switch S1. This
starts a new switch cycle. The ramp signal, composed of
both artificial ramp and output ripple, eventually comes
across the VC voltage, and consequently resets the latch to
turn off the switch. The switch S1 will turn on again at the
beginning of the next switch cycle. In a buck converter, the
output ripple is determined by the ripple current of the
inductor L1 and the ESR (equivalent series resistor) of the
output capacitor C1.
An external clock signal can sync CS51411/ 14 to a higher
frequency. The rising edge of the sync pulse turns on the
power switch to start a new switching cycle, as shown in
Figure 2. There is approximately 0.5µs delay between the
rising edge of the sync pulse and rising edge of the VSW
pin voltage. The sync threshold is TTL logic compatible,
and duty cycle of the sync pulses can vary from 10% to
90%. The frequency foldback feature is disabled during the
sync mode.
The slope compensation signal is a fixed voltage ramp pro-
vided by the oscillator. Adding this signal eliminates sub-
harmonic oscillation associated with the operation at duty
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
