Application Information: continued
minimizes inrush currents during regulator power-up, and
switcher output enable.
the 1.06V PWM comparator offset, the regulator output will
softstart normally (see Figure 5).
Because the start-up circuitry depends on the current sense
function, a current sense resistor should always be used.
Start-up
The CS5132 provides a controlled start-up of regulator out-
put voltage and features Programmable Soft Start imple-
mented through the Error Amp and external Compensation
Capacitor. This feature, combined with overcurrent protec-
tion, prevents stress to the regulator power components
and overshoot of the output voltage during start-up.
Start-up @
V
CC > 8.4V
As Power is applied to the regulator, the CS5132
Undervoltage Lockout circuit (UVL) monitors the ICs sup-
ply voltage (VCC) which is typically connected to the +12V
output of the AC-DC power supply. The UVL circuit pre-
vents the NFET gates from being activated until VCC
exceeds the 8.4V (typ) threshold. Hysteresis of 300mV (typ)
is provided for noise immunity. The Error Amp Capacitor
connected to the COMP pin is charged by a 30µA current
source. This capacitor must be charged to 1.06V (typ) so
that it exceeds the PWM comparatorÕs offset before the V2
PWM control loop will permit switching to occur.
When VCC has exceeded 8.4V and COMP has charged to
1.06V, the upper Gate driver (GATE(H)) is activated, turn-
ing on the upper FET. This causes current to flow through
the output inductor and into the output capacitors and load
according to the following equation:
Figure 2: Normal Start-up (2ms/div).
Channel 1 - Regulator Output Voltage (1V/div)
Channel 2 - COMP Pin (1V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
T
I = (VIN Ð VOUT) x
L
GATE(H) and the upper NFET remain on and inductor cur-
rent ramps up until the initial pulse is terminated by either
the PWM control loop or the overcurrent protection. This
initial pulse of in-rush current minimizes start-up time, but
does not overstress the regulatorÕs power components.
The PWM comparator will terminate the initial pulse if the
regulator output exceeds the voltage on the COMP pin
minus the 1.06V PWM comparator offset prior to the drop
across the current sense resistor exceeding the current limit
threshold. In this case, the PWM control loop has achieved
regulation and the initial pulse is then followed by a con-
stant off time as programmed by the COFF capacitor. The
COMP capacitor will continue to slowly charge and regula-
tor output voltage will follow it, less the 1.06V PWM offset,
until it achieves the voltage programmed by the DACÕs VID
input. The Error Amp will then source or sink current to the
COMP cap as required to maintain the correct regulator DC
output voltage. Since the rate of increase of the COMP pin
voltage is typically set much slower than the regulatorÕs
slew capability, inrush current, output voltage, and duty
cycle all gradually increase from zero. (See Figures 2, 3,
and 4.)
If the voltage across the Current Sense resistor generates a
voltage difference between the VFFB and VOUT pins that
exceeds the OVC Comparator Offset Voltage (86mV typi-
cal), the Fault latch is set. This causes the COMP pin to be
quickly discharged, turning off GATE(H) and the upper
NFET since the voltage on the COMP pin is now less than
the 1.06V PWM comparator offset. The Fault latch is reset
when the voltage on the COMP decreases below the
Discharge threshold voltage (0.25V typical). The COMP
capacitor will again begin to charge, and when it exceeds
Start-up @
VCC > 8.4V
Initial Pulse until VOUT
> COMP - PWM Offset
Figure 3: Normal Start-up showing initial pulse followed by Soft Start
(20µs/div).
Channel 1 - Regulator Output Voltage (0.2V/div)
Channel 2 Ð Inductor Switching Node (5V/div)
Channel 3 - VCC (10V/div)
Channel 4 - Regulator Input Voltage (5V/div)
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
