Circuit Description: continued
The logic state of the LATCH can be changed only when
Theory of Operation
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse VSY, gate G2 output goes high, resetting the
latch at time t3. Capacitor CR is discharged through tran-
sistor Q4. CRÕs output goes low disabling the output stage,
and the external power switch (an N-FET) is turned off.
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The VFB voltage is monitored by the error amplifier EA. It
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is com-
pared at the PWM comparator with the ramp voltage
generated by capacitor CR. When the ramp voltage VR,
exceeds the control voltage VC, the output of the PWM
comparator goes high, latching its state through the
LATCH, the output stage transistor Q1 turns on, and the
external power switch, usually an N-FET, turns on.
RAMP Function
The value of the ramp capacitor CR is based on the
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse VSY
.
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100µA, and the IC is in SLEEP mode.
SYNC Function
The SYNC circuit is activated at time t1 (Figure 1) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capac-
itor CR is allowed to charge through the internal current
source I (200µA). At time t2, the ramp voltage intersects
with the control voltage VC and the output of the PWM
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
FAULT Function
The voltage at the VCC pin is monitored by the undervolt-
age lockout comparator with hysteresis. When VCC falls
below the UVL threshold, the 5V reference and all the cir-
cuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500µA.
The VCC supply voltage is further monitored by the
VCC OK comparator. When VCC is reduced below
_
VREF - 0.7V, a fault signal is sent to gate G1. This fault sig-
nal, which determines if VCC is absent, works in conjunc-
tion with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from over-
voltage stress. This is accomplished through gate G1 by
driving transistor Q4 on.
V
SY
V
SY
1
2
0V
V
V
C
RAMP
V
+ V
SY
D
V
DS
3
0V
V
SY
V
D
_
An additional fault signal is derived from the REF OK
V
V
S
4
0V
comparator. VREF is monitored so to disable the output
through gate G1 when the VREF voltage falls below the
V
Ð V
OUT
SY
V
L1
G
_
_
OK threshold. As in the VCC OK fault, the REF OK fault
disables the output after the current cycle has been com-
pleted. The fault logic will operate normally only when
_
0V
V
+ V
D
OUT
V
5
+ V
SY
C
D
V
V
REF voltage is within the specification limits of REF OK.
6
0V
Ground Level
(Gate doesn't go
below Gnd)
t
t
t
3
t
4
t
1
1
2
DRAIN Function
The drain pin, VD monitors the voltage on the drain of the
power switch and derives energy from it to keep the out-
put stage in an off state when VC or VCC is below the min-
imum specified voltage.
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
