Package Pin Description
PIN SYMBOL
PACKAGE PIN #
14L PDIP 16L SO Wide
FUNCTION
1
2
1
2
3
SYNC
VCC
Synchronization input.
Logic supply (10V to 45V).
3
VREF
LGnd
VFB
5.0V voltage reference.
4
Logic level ground (Analog and digital ground tied).
Error amplifier inverting input.
5
6
7
6
COMP
RAMP
IS+
Error amplifier output and compensation.
RAMP programmable with the external capacitor.
Current sense amplifier non-inverting input.
Current sense amplifier inverting input.
Current sense amplifier compensation and output.
Power ground.
7
8
8
9
9
10
11
12, 13
14
15
16
5
IS-
10
11
12
13
14
IS COMP
PGnd
VG
External power switch gate drive.
Output power stage supply voltage (8V to 75V).
External FET DRAIN Voltage Monitor.
Analog Ground.
VC
VD
AGnd
DGnd
4
Digital Ground.
Circuit Description
Block Diagram
VCC
VD
VC
VCC
REF
+
+
Ð
+
Q1
Q2
+
SLEEP
Ð
VREF
5V
OK
UVL
VG
+
8V/7V
LGnd
0.7V
Ð
PGnd
Ð
IS COMP
VCC
5V
EA
5V
24.6k
Ð
+
IS-
IS
VFB
Ð
+
IS+
Ð
VC
5V
10k
10k
BUF
Ð
Ð
+
+
PWM
+
+
2V
Q3
Ð
+
2.4V
5V
COMP
RAMP
Ð
5V
Q
Q
S
R
I = 200mA
LATCH
+
Ð
0.7V
+
5V
Ð
1.5V
Ð
_
VCC OK
+
+
5V
RAMP
+
Ð
Q4
G1
_
REF OK
+
Ð
Ð
1.65V
VCC
5V
+
4.5V/4.4V
Ð
SYNC
+
G2
SYNC
Ð
+
Ð
2.5V
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
