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CS4172 参数 Datasheet PDF下载

CS4172图片预览
型号: CS4172
PDF下载: 下载PDF文件 查看货源
内容描述: 单空芯仪表驱动器 [Single Air-Core Gauge Driver]
分类和应用: 驱动器仪表
文件页数/大小: 6 页 / 162 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Applications Information: continued  
To drive the gaugeÕs pointer to a particular angle, the  
register changes at SO on the falling edge of SCLK. This  
arrangement allows the cascading of devices. SO is  
always enabled. Data shifts through without affecting the  
outputs until CS is brought low. At this time the internal  
DAC is updated and the outputs change accordingly.  
microcontroller sends a 10-bit digital word into the serial  
port. These 10 bits are divided as shown in Figure 2.  
However, from a software programmers viewpoint, a  
360¡ circle is divided into 1024 equal parts of .35¡ each.  
Table 1 shows the data associated with the 45¡ divisions  
of the 360¡ driver.  
CS  
CSHold  
CSSetup  
MSB  
D9  
LSB  
D0  
SCLK  
Major  
Gauge  
(360°)  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
SI(Setup)  
SI(Hold)  
D9 Ð D7 select  
which octant  
Divides a 45° octant into 128 equal parts  
to achieve a .35° resolution  
Code 0 Ð 12710  
SI  
Figure 2. Definition of serial word.  
SO(Rise, Fall)  
10% - 90%  
SO  
SO(tpd)  
Input Code  
(Decimal) Degrees  
Ideal  
Nominal  
Degrees  
VSIN  
(V)  
VCOS  
(V)  
Figure 3. Serial data timing diagram.  
0
0
45  
90  
135  
180  
225  
270  
315  
359.65  
0.176  
45.176  
90.176  
135.176  
180.176  
225.176  
270.176  
315.176  
359.826  
0.032  
10.476  
10.476  
10.412  
-0.032  
-10.476  
-10.476  
-10.476  
-0.032  
10.476  
10.412  
-0.032  
-10.476  
-10.476  
-10.412  
0.032  
128  
256  
384  
512  
640  
768  
896  
1023  
VCC  
CS  
SI  
10 Bits  
10 Bits  
10.476  
10.476  
OE  
ST  
Table 1. Nominal output for major gauge (VBB = 14V).  
The 10 bits are shifted into the deviceÕs shift register MSB  
first using an SPI compatible scheme. This method is  
shown in Figure 3. The CS must be high and remain high  
for SCLK to be enabled. Data on SI is shifted in on the ris-  
ing edge of the synchronous clock signal. Data in the shift  
OUTPUTS  
ENABLED  
OUTPUTS  
ENABLED  
Figure 4. Power-up sequence.  
Application Diagram  
VBAT  
5V  
VREG  
12V  
CS-8156  
ENABLE  
360° Gauge  
SIN-  
10k  
COS+  
COS-  
VBB  
SIN+  
ST  
VCC  
CS  
SI  
SCLK  
CS4172  
Microcontroller  
SO  
Next Driver  
OE  
5