Electrical Characteristics: -40¡C ² TA ² 105¡C; 7.5V ² VBB ² 14V; 4.5V ² VCC ² 5.5V (unless otherwise specified)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shift Clock Frequency
SCLK High Time
SCLK Low Time
SO Rise Time
2.0
MHz
ns
175
175
ns
0.75V to VCC - 1.2V; CL = 90pF
0.75V to VCC - 1.2V; CL = 90pF
CL = 90pF
150
150
150
ns
SO Fall Time
ns
SO Delay Time
SI Setup Time
ns
75
75
0
ns
SI Hold Time
ns
CS Setup Time
CS Hold Time
ns
75
ns
Package Pin Description
PACKAGE PIN#
PIN SYMBOL
FUNCTION
16 Lead SO Wide
16 Lead PDIP
1
1
SIN-
SIN+
VBB
Gnd
SI
Negative output for SINE coil.
Positive output for SINE coil.
Analog supply. Nominally 13.5V.
Ground.
2
2
3
4,5,12,13
6
4
3,13,14
6
Serial data input. Data present at the rising edge of the
clock signal is shifted into the internal shift register.
7
7
VCC
5V logic supply. The internal registers and latches are
reset by a POR generated by the rising edge of the voltage
on this pin.
8
9
8
9
OE
Controls the state of the output buffers. A logic low on
this pin turns them off.
SCLK
Serial clock for shifting in/out of data. Rising edge shifts
data on SI into the shift register and the falling edge
changes the data on SO.
10
10
CS
When high allows data at SI to be shifted into part with
the rising edges of SCLK. The falling edge transfers the
shift register contents into the DAC and multiplexer to
update the output buffers. The falling edge also re-enables
the output drivers if they have been disabled by a fault.
11
14
11
5
ST
STATUS reflects the state of the outputs and is low any-
time the outputs are disabled, either by OE or the internal
protection circuitry. Requires external pull-up resistor.
SO
Serial data output. Existing 10-bit data is shifted out when
new data is shifted in. Allows cascading of multiple
devices on common serial port.
15
16
15
16
12
COS-
COS+
NC
Negative output for COSINE coil.
Positive output for COSINE coil.
No connection.
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
