24LLC16
16K-Bit-Serial EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The 24LLC16 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that gets data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Only one 24LLC16 devices can be connected to the I2C-bus as slaves (see Figure 5-
6). Both the master and slaves can operate as a transmitter or a receiver, but the master device determines
which bus operating mode would be active.
VCC
VCC
R
R
SDA
SCL
Master
Bus Master
Slave
(Transmitter/
Receiver)
24LLC16
Figure 5-6. Typical Configuration
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.5, 2002
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