24LLC16
16K-Bit-Serial EEPROM
SDA
WP
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
EEPROM
Cell Array
2,048 x 8 bits
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
A0
A1
A2
Column Decoder
Data Register
DOUT and ACK
Figure 5-1. 24LLC16 Block Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
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Rev 1.0 Aug.5, 2002
Page 2 of 22
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