24LLC08
8K-Bit Serial EEPROM
tF
tHIGH
tR
tLOW
SCL
SDA In
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
tAA
SDA Out
Figure 3-15. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
ACK
WORDn
tWR
Stop
Condition
Start
Condition
Figure 3-16. Write Cycle Timing Diagram
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Nov. 18, 2002
Page 16 of 19
Fax:886-3-3521052