欢迎访问ic37.com |
会员登录 免费注册
发布采购

24LLC08A 参数 Datasheet PDF下载

24LLC08A图片预览
型号: 24LLC08A
PDF下载: 下载PDF文件 查看货源
内容描述: [EEPROM, 1KX8, Serial, CMOS, PDSO8,]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
文件页数/大小: 19 页 / 377 K
品牌: CERAMATE [ CERAMATE TECHNICAL ]
 浏览型号24LLC08A的Datasheet PDF文件第11页浏览型号24LLC08A的Datasheet PDF文件第12页浏览型号24LLC08A的Datasheet PDF文件第13页浏览型号24LLC08A的Datasheet PDF文件第14页浏览型号24LLC08A的Datasheet PDF文件第16页浏览型号24LLC08A的Datasheet PDF文件第17页浏览型号24LLC08A的Datasheet PDF文件第18页浏览型号24LLC08A的Datasheet PDF文件第19页  
24LLC08  
8K-Bit Serial EEPROM  
Table 3-4. D.C. Electrical Characteristics (Continued)  
°
°
°
°
(TA = – 25 C to + 70 C (C), – 40 C to + 85 C (I), VCC = 1.8 V to 5.5 V)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
CIN  
10  
pF  
°
Input capacitance  
25 C, 1MHz,  
VCC = 5 V, VIN = 0 V,  
A0, A1, A2, SCL and WP pin  
CI/O  
10  
°
Input/output capacitance  
25 C, 1MHz,  
VCC = 5 V, VI/O = 0 V,  
SDA pin  
Table 3-5. A.C. Electrical Characteristics  
°
°
°
°
(TA = – 25 C to + 70 C (C), – 40 C to + 85 C (I), VCC = 1.8 V to 5.5 V)  
Parameter  
Symbol Conditions  
VCC = 1.8 to 5.5 V  
(Standard Mode)  
VCC = 2.5 to 5.5 V  
(Fast Mode)  
Unit  
Min  
Max  
Min  
Max  
FCLK  
tHIGH  
tLOW  
External clock frequency  
Clock high time  
0
100  
0
400  
kHz  
4
4.7  
0.6  
1.3  
ms  
Clock low time  
tR  
Rising time  
SDA, SCL  
1
0.3  
0.3  
tF  
Falling time  
SDA, SCL  
0.3  
tHD:STA  
tSU:STA  
tHD:DAT  
tSU:DAT  
tSU:STO  
tBUF  
Start condition hold time  
Start condition setup time  
Data input hold time  
Data input setup time  
Stop condition setup time  
Bus free time  
4
0.6  
0.6  
0
4.7  
0
0.25  
4
0.1  
0.6  
1.3  
Before new  
4.7  
transmission  
tAA  
Data output valid from  
clock low (note)  
0.3  
3.5  
0.9  
tSP  
Noise spike width  
Write cycle time  
100  
5
50  
5
ns  
tWR  
ms  
NOTES:  
1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available.  
2. When acting as a transmitter, the 24LLC08 must provide an internal minimum delay time to bridge the undefined  
period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or  
stop condition.  
* All specs and applications shown above subject to change without prior notice.  
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN  
Tel:886-3-3214525  
Email: server@ceramate.com.tw  
Http: www.ceramate.com.tw  
Rev 1.0 Nov. 18, 2002  
Page 15 of 19  
Fax:886-3-3521052  
 复制成功!