24LLC02
2K-Bits Serial EEPROM For Low Power
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The 24LLC02 supports the I 2 C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions
, controlling bus access. Using the A0, A1, and A2 input pins, up to eight 24LLC02 devices can be connected
to the same I 2 C-bus as slaves (see Figure 1-6). Both the master and slaves can operate as transmitter or receiver
, but the master device determines which bus operating mode would be active.
VCC
VCC
SDA
SCL
Slave 1
24LLC02
Slave 2
Slave 3
24LLC02
Slave 8
24LLC02
24LLC02
2 4 2 L L C
Bus Master
(Transmitter/
Receiver)
Tx/Rx
A0 A1 A2
Tx/Rx
Tx/Rx
A0 A1 A2
Tx/Rx
A0 A1 A2
A0 A1 A2
MCU
To V CC or V SS
To V CC or V SS
To V CC or V SS
To V CC or V SS
Figure 1-6. Typical Configuration (16 Kbits of Memory on the I 2 C-Bus)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.0 Dec. 26, 2001
Page 5 of 19
Fax:886-3-3521052
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