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NEZ5964-4D 参数 Datasheet PDF下载

NEZ5964-4D图片预览
型号: NEZ5964-4D
PDF下载: 下载PDF文件 查看货源
内容描述: [RF Power Field-Effect Transistor, 1-Element, C Band, Gallium Arsenide, N-Channel, Metal Semiconductor FET, HERMETIC SEALED, T-61, 2 PIN]
分类和应用: 局域网晶体管
文件页数/大小: 6 页 / 65 K
品牌: CEL [ CALIFORNIA EASTERN LABS ]
 浏览型号NEZ5964-4D的Datasheet PDF文件第2页浏览型号NEZ5964-4D的Datasheet PDF文件第3页浏览型号NEZ5964-4D的Datasheet PDF文件第4页浏览型号NEZ5964-4D的Datasheet PDF文件第5页浏览型号NEZ5964-4D的Datasheet PDF文件第6页  
C-BAND INTERNALLY
MATCHED POWER GaAs MESFET
FEATURES
HIGH P
OUT
18W (42.5 dBm) Typ P
1dB
for NEZ5964-15D/15DL
9W (39.5 dBm) Typ P
1dB
for NEZ5964-8D/8DL
4.5W (36.5 dbm) Typ P
1dB
for NEZ5964-4D/4DL
HIGH EFFICIENCY
37%
η
ADD
for 4.5W Device
35%
η
ADD
for 9W Device
33%
η
ADD
for 18W Device
LOW IMD
-45 dBc IM
3
@ 31.5 dBm P
OUT
(SCL) -15DL
-45 dBc IM
3
@ 29 dBm P
OUT
(SCL) -8DL
-45 dBc IM
3
@ 26 dBm P
OUT
(SCL) -4DL
SiO
2
PASSIVATED CHIP
For Power/Gain Stability Under RF Overdrive
CLASS A OPERATION
INTERNALLY MATCHED (IN/OUT)
SUPERIOR GAIN FLATNESS
INDUSTRY COMPATIBLE HERMETIC PACKAGES
= 25°C)
NEZ5964-4D
NEZ5964-4DL
T-61
UNITS MIN
dBm
dBm
dBm
%
A
dB
dBc
dBc
dBc
A
V
V
V
V
V
V
mS
mS
mS
°C/W
°C
35.5
NEZ5964-8D
NEZ5964-8DL
T-61
45
NEZ5964-15D
NEZ5964-15DL
NEZ5964-8D
NEZ5964-8DL
NEZ5964-4D
NEZ5964-4DL
OUTPUT POWER AND EFFICIENCY
vs. INPUT POWER
100%
-15D
-8D
40
P
OUT
-4D
35
60%
80%
-4D
30
-8D
-15D
25
Efficiency
20
12
17
22
27
32
37
0%
20%
40%
Input Power, P
IN
(dBm)
ELECTRICAL CHARACTERISTICS
(T
C
PART NUMBER
PACKAGE OUTLINE
SYMBOLS PARAMETERS AND CONDITIONS
P
1dB
Output Power at P
IdB1
I
DSQ
= 0.8A, (RF Off)
I
DSQ
= 1.6A
I
DSQ
= 4.0A
NEZ5964-15D
NEZ5964-15DL
T-65
TYP MAX TEST CONDITIONS
V
DS
= 10V
f = 5.9
to 6.45 GHz
6.0
Zs = Z
L
50 ohms
V
DS
= I0V
f
1
= 6.44 GHz
f
2
= 6.45 GHZ
2 Equal Tones
TYP MAX MIN
36.5
38.5
37
1.1
10.0
-45
TYP MAX MIN
39.5
41.5
42.5
33
4.4
9.0
35
2.2
9.5
Power Added Efficiency @ P
1dB
I
DS
Drain Current at P
1dB
Linear Gain
G
L
IM
3
3rd Order Intermodulation Distortion
3
at
-XDL Pout = 26 dBm SCL
2
, I
DSQ
= 0.5 x I
DSS
Option Pout = 29 dBm SCL
2
, I
DSQ
= 0.5 x I
DSS
Only Pout = 31.5 dBm SCL
2
, I
DSQ
= 0.5 x I
DSS
I
DSS
Saturated Drain Current, V
GS
= 0 V
V
P
Pinch Off Voltage
I
DS
= 15 mA
I
DS
= 30 mA
I
DS
= 60 mA
BV
DGO
Drain - Gate Breakdown Voltage
I
DG
= 15 mA
I
DG
= 30 mA
I
DG
= 60 mA
g
m
Transconductance
I
DS
= I A
I
DS
= 2 A
I
DS
= 4 A
R
TH(CH-C)
Thermal Resistance (Channel to Case)
∆T
(CH-C)
Channel Temperature Rise
4
η
ADD
1.5
8.5
-42
3.0
8.0
9.0
-45
1.0
-3.5
2.3
-2.0
3.5
-0.5
-3.5
-2.0
2.0
4.5
-42
7.0
4.0
-45
9.2
-42
14.0
V
DS
= 2.5 V
-0.5
-3.5
-2.2
-0.5
20
22
20
22
20
1300
2600
5.0
6.0
48
2.5
3.0
48
5200
1.3
1.5
60
22
Notes:
1. P
1dB
: Ouptut Power at the 1dB Gain Compression Point.
2. SCL: Single Carrier Level.
3. Maximum Spec Applies to -XDL Option Only.
4.
∆T
(CH-C)
= T
CH
- T
C
= 10 V x I
DSQ
x R
TH (CH-C) MAX
.
California Eastern Laboratories
Power Added Efficiency,
η
ADD
(%)
Output Power, P
OUT
(dBm)