ISG3300EU
VCO CHARACTERISTICS
Serial Data Input Timing
(1)
DATA N20: WSB
(R20: WSB)
N19
N10
N9
C2
C1: LSB
(R19)
(R10) (R9) (R8) (C2)
(C1: LSB)
CLOCK
tCWL
LE
t
ES
t
CS
t
CH
t
CWH
tEW
OR
LE
(2)
Notes:
VCO Input Voltage
Table 3. The FOLD Output Truth Table
RF1 R (19) RF2 R (19) RF1 R (20) RF2 R (20)
1. Parenthesis data indicates programmable reference
divider data.
2. Data shifted into register on clock rising edge.
3. Data is shifted in MSB first.
FOLD
(RF1 LD) (RF2 LD)
(RF1 FO)
(RF2 FO) Output State
0
0
0
1
0
0
0
0
Disabled1
Test Conditions:
RF2 Lock
The Serial Data Input Timing is tested using a symmetrical
waveform around VCC/2. The test waveform has an edge
rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and
2.6 V @ VCC = 5.5 V.
Detect2
1
1
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
RF1 Lock
Detect2
RF1/RF2
Lock Detect2
RF2 Reference
Divider Output
RF1 Reference
Divider Output
RF2
Phase Comparator and Internal Charge Pump Character-
istics.
X
X
X
Programmable
Divider Output
RF1
f
r
f
p
X
1
1
0
Programmable
Divider Output
Fastlock3
For internal
use only
LD
0
0
0
1
1
1
1
1
H
D
o
Z
L
1
1
0
1
1
1
1
1
For internal
use only
Counter Reset4
f
> f
f
= f
f
< f
f
< f
f < f
r p
r
p
r
p
r
p
r
p
X - Don’t care condition
Notes:
1. Phase difference detection range: -2π to +2π
Notes:
1. When the FOLD output is disabled, it is actively pulled to a
low logic state.
2. The minimum width pump up and pump down current pulses
occur at the DO pin when the loop is locked.
2. Lock detect output provided to indicate when the VCO fre-
quency is in “lock”. When the loop is locked and a lock
detect mode is selected, the pin's output is HIGH, with nar-
row pulses LOW. In the RF1/RF2 lock detect mode a locked
condition is indicated when RF2 and RF1 are both locked.
3. The Fastlock mode utilized the FOLD output pin to switch a
second loop filter damping resistor to ground during fastlock
operation. Activation of Fastlock occurs whenever the RF
loop’s Icpo magnitude bit #17 is selected HIGH (while the
#19 and #20 mode bits are set for Fastlock).
4. The Counter Reset mode bits R19 and R20 when activated
reset all counters. Upon removal of the Reset bits the N
counter resumes counting in “close” alignment with R
counter. (The maximum error is one prescaler cycle). If
the Reset bits are activated the R counter is also forced to
Reset, allowing smooth acquisition upon powering up.
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THIS PRODUCT HAS PATENT PENDING
DATA SUBJECT TO CHANGE WITHOUT NOTICE
PRINTED IN USA -5/99
CEL [ CALIFORNIA EASTERN LABS ]
